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Searched refs:cw5 (Results 1 – 14 of 14) sorted by relevance

/linux/drivers/gpu/drm/amd/display/dmub/src/
H A Ddmub_dcn30.c126 const struct dmub_window *cw5, in dmub_dcn30_setup_windows() argument
178 offset = cw5->offset; in dmub_dcn30_setup_windows()
182 REG_WRITE(DMCUB_REGION3_CW5_BASE_ADDRESS, cw5->region.base); in dmub_dcn30_setup_windows()
184 DMCUB_REGION3_CW5_TOP_ADDRESS, cw5->region.top, in dmub_dcn30_setup_windows()
191 cw5->region.top - cw5->region.base - 1, in dmub_dcn30_setup_windows()
H A Ddmub_dcn20.c193 const struct dmub_window *cw5, in dmub_dcn20_setup_windows() argument
248 dmub_dcn20_translate_addr(&cw5->offset, fb_base, fb_offset, &offset); in dmub_dcn20_setup_windows()
252 REG_WRITE(DMCUB_REGION3_CW5_BASE_ADDRESS, cw5->region.base); in dmub_dcn20_setup_windows()
254 DMCUB_REGION3_CW5_TOP_ADDRESS, cw5->region.top, in dmub_dcn20_setup_windows()
261 cw5->region.top - cw5->region.base - 1, in dmub_dcn20_setup_windows()
H A Ddmub_dcn31.c189 const struct dmub_window *cw5, in dmub_dcn31_setup_windows() argument
213 offset = cw5->offset; in dmub_dcn31_setup_windows()
217 REG_WRITE(DMCUB_REGION3_CW5_BASE_ADDRESS, cw5->region.base); in dmub_dcn31_setup_windows()
219 DMCUB_REGION3_CW5_TOP_ADDRESS, cw5->region.top, in dmub_dcn31_setup_windows()
226 cw5->region.top - cw5->region.base - 1, in dmub_dcn31_setup_windows()
H A Ddmub_dcn32.c218 const struct dmub_window *cw5, in dmub_dcn32_setup_windows() argument
242 offset = cw5->offset; in dmub_dcn32_setup_windows()
246 REG_WRITE(DMCUB_REGION3_CW5_BASE_ADDRESS, cw5->region.base); in dmub_dcn32_setup_windows()
248 DMCUB_REGION3_CW5_TOP_ADDRESS, cw5->region.top, in dmub_dcn32_setup_windows()
255 cw5->region.top - cw5->region.base - 1, in dmub_dcn32_setup_windows()
H A Ddmub_dcn401.c192 const struct dmub_window *cw5, in dmub_dcn401_setup_windows() argument
216 offset = cw5->offset; in dmub_dcn401_setup_windows()
220 REG_WRITE(DMCUB_REGION3_CW5_BASE_ADDRESS, cw5->region.base); in dmub_dcn401_setup_windows()
222 DMCUB_REGION3_CW5_TOP_ADDRESS, cw5->region.top, in dmub_dcn401_setup_windows()
229 cw5->region.top - cw5->region.base - 1, in dmub_dcn401_setup_windows()
H A Ddmub_dcn35.c231 const struct dmub_window *cw5, in dmub_dcn35_setup_windows() argument
255 offset = cw5->offset; in dmub_dcn35_setup_windows()
259 REG_WRITE(DMCUB_REGION3_CW5_BASE_ADDRESS, cw5->region.base); in dmub_dcn35_setup_windows()
261 DMCUB_REGION3_CW5_TOP_ADDRESS, cw5->region.top, in dmub_dcn35_setup_windows()
268 cw5->region.top - cw5->region.base - 1, in dmub_dcn35_setup_windows()
H A Ddmub_dcn30.h45 const struct dmub_window *cw5,
H A Ddmub_srv.c624 struct dmub_window cw0, cw1, cw2, cw3, cw4, cw5, cw6, region6; in dmub_srv_hw_init() local
696 cw5.offset.quad_part = tracebuff_fb->gpu_addr; in dmub_srv_hw_init()
697 cw5.region.base = DMUB_CW5_BASE; in dmub_srv_hw_init()
698 cw5.region.top = cw5.region.base + tracebuff_fb->size; in dmub_srv_hw_init()
718 dmub->hw_funcs.setup_windows(dmub, &cw2, &cw3, &cw4, &cw5, &cw6, &region6); in dmub_srv_hw_init()
H A Ddmub_dcn20.h199 const struct dmub_window *cw5,
H A Ddmub_dcn31.h201 const struct dmub_window *cw5,
H A Ddmub_dcn32.h208 const struct dmub_window *cw5,
H A Ddmub_dcn35.h221 const struct dmub_window *cw5,
H A Ddmub_dcn401.h217 const struct dmub_window *cw5,
/linux/drivers/gpu/drm/amd/display/dmub/
H A Ddmub_srv.h395 const struct dmub_window *cw5,