Home
last modified time | relevance | path

Searched refs:cur0_ctl (Results 1 – 5 of 5) sorted by relevance

/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn35/
H A Ddcn35_hwseq.c1705 p->CNVC_CUR0_CURSOR0_CONTROL__CUR0_ENABLE = dpp->att.cur0_ctl.bits.cur0_enable; in dcn35_update_cursor_offload_pipe()
1706 p->CNVC_CUR0_CURSOR0_CONTROL__CUR0_MODE = dpp->att.cur0_ctl.bits.mode; in dcn35_update_cursor_offload_pipe()
1707 p->CNVC_CUR0_CURSOR0_CONTROL__CUR0_EXPANSION_MODE = dpp->att.cur0_ctl.bits.expansion_mode; in dcn35_update_cursor_offload_pipe()
1708 p->CNVC_CUR0_CURSOR0_CONTROL__CUR0_ROM_EN = dpp->att.cur0_ctl.bits.cur0_rom_en; in dcn35_update_cursor_offload_pipe()
/linux/drivers/gpu/drm/amd/display/dc/dpp/dcn30/
H A Ddcn30_dpp.c432 dpp_base->att.cur0_ctl.bits.expansion_mode = 0; in dpp3_set_cursor_attributes()
433 dpp_base->att.cur0_ctl.bits.cur0_rom_en = cur_rom_en; in dpp3_set_cursor_attributes()
434 dpp_base->att.cur0_ctl.bits.mode = color_format; in dpp3_set_cursor_attributes()
/linux/drivers/gpu/drm/amd/display/dc/
H A Ddc_dmub_srv.c1077 pl->position_cfg.pDpp.cur0_ctl.raw = dpp->pos.cur0_ctl.raw; in dc_build_cursor_position_update_payload0()
1093 pl_A->aDpp.cur0_ctl.raw = dpp->att.cur0_ctl.raw; in dc_build_cursor_attribute_update_payload1()
/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn401/
H A Ddcn401_hwseq.c3014 p->CM_CUR0_CURSOR0_CONTROL__CUR0_ENABLE = dpp->att.cur0_ctl.bits.cur0_enable; in dcn401_update_cursor_offload_pipe()
3015 p->CM_CUR0_CURSOR0_CONTROL__CUR0_MODE = dpp->att.cur0_ctl.bits.mode; in dcn401_update_cursor_offload_pipe()
3016 p->CM_CUR0_CURSOR0_CONTROL__CUR0_EXPANSION_MODE = dpp->att.cur0_ctl.bits.expansion_mode; in dcn401_update_cursor_offload_pipe()
3017 p->CM_CUR0_CURSOR0_CONTROL__CUR0_ROM_EN = dpp->att.cur0_ctl.bits.cur0_rom_en; in dcn401_update_cursor_offload_pipe()
/linux/drivers/gpu/drm/amd/display/dmub/inc/
H A Ddmub_cmd.h4070 union dmub_reg_cur0_control_cfg cur0_ctl; member
4103 union dmub_reg_cur0_control_cfg cur0_ctl; member