Home
last modified time | relevance | path

Searched refs:ctrl_reg (Results 1 – 25 of 67) sorted by relevance

123

/linux/drivers/watchdog/
H A Dmachzwd.c188 unsigned int ctrl_reg = 0; in zf_timer_off() local
196 ctrl_reg = zf_get_control(); in zf_timer_off()
197 ctrl_reg |= (ENABLE_WD1|ENABLE_WD2); /* disable wd1 and wd2 */ in zf_timer_off()
198 ctrl_reg &= ~(ENABLE_WD1|ENABLE_WD2); in zf_timer_off()
199 zf_set_control(ctrl_reg); in zf_timer_off()
211 unsigned int ctrl_reg = 0; in zf_timer_on() local
227 ctrl_reg = zf_get_control(); in zf_timer_on()
228 ctrl_reg |= (ENABLE_WD1|zf_action); in zf_timer_on()
229 zf_set_control(ctrl_reg); in zf_timer_on()
238 unsigned int ctrl_reg = 0; in zf_ping() local
[all …]
H A Dmeson_gxbb_wdt.c166 u32 ctrl_reg; in meson_gxbb_wdt_probe() local
194 ctrl_reg = readl(data->reg_base + GXBB_WDT_CTRL_REG) & in meson_gxbb_wdt_probe()
197 if (ctrl_reg) { in meson_gxbb_wdt_probe()
207 ctrl_reg |= ((clk_get_rate(data->clk) / 1000) & in meson_gxbb_wdt_probe()
213 writel(ctrl_reg, data->reg_base + GXBB_WDT_CTRL_REG); in meson_gxbb_wdt_probe()
/linux/drivers/clk/microchip/
H A Dclk-core.c91 void __iomem *ctrl_reg; member
101 return readl(pb->ctrl_reg) & PB_DIV_ENABLE; in pbclk_is_enabled()
108 writel(PB_DIV_ENABLE, PIC32_SET(pb->ctrl_reg)); in pbclk_enable()
116 writel(PB_DIV_ENABLE, PIC32_CLR(pb->ctrl_reg)); in pbclk_disable()
147 return ((readl(pb->ctrl_reg) >> PB_DIV_SHIFT) & PB_DIV_MASK) + 1; in pbclk_read_pbdiv()
174 err = readl_poll_timeout(pb->ctrl_reg, v, v & PB_DIV_READY, in pbclk_set_rate()
185 v = readl(pb->ctrl_reg); in pbclk_set_rate()
191 writel(v, pb->ctrl_reg); in pbclk_set_rate()
196 err = readl_poll_timeout(pb->ctrl_reg, v, v & PB_DIV_READY, in pbclk_set_rate()
226 pbclk->ctrl_reg = desc->ctrl_reg + core->iobase; in pic32_periph_clk_register()
[all …]
H A Dclk-core.h21 const u32 ctrl_reg; member
38 const u32 ctrl_reg; member
45 const u32 ctrl_reg; member
/linux/drivers/bluetooth/
H A Dbluecard_cs.c79 unsigned char ctrl_reg; member
265 info->ctrl_reg |= REG_CONTROL_RTS; in bluecard_write_wakeup()
266 outb(info->ctrl_reg, iobase + REG_CONTROL); in bluecard_write_wakeup()
307 info->ctrl_reg &= ~0x03; in bluecard_write_wakeup()
308 info->ctrl_reg |= baud_reg; in bluecard_write_wakeup()
309 outb(info->ctrl_reg, iobase + REG_CONTROL); in bluecard_write_wakeup()
312 info->ctrl_reg &= ~REG_CONTROL_RTS; in bluecard_write_wakeup()
313 outb(info->ctrl_reg, iobase + REG_CONTROL); in bluecard_write_wakeup()
512 info->ctrl_reg &= ~REG_CONTROL_INTERRUPT; in bluecard_interrupt()
513 outb(info->ctrl_reg, iobase + REG_CONTROL); in bluecard_interrupt()
[all …]
/linux/drivers/thermal/
H A Dloongson2_thermal.c45 void __iomem *ctrl_reg; member
55 int ctrl_reg = low ? LOONGSON2_THSENS_CTRL_LOW_REG : LOONGSON2_THSENS_CTRL_HI_REG; in loongson2_set_ctrl_regs() local
59 writew(reg_ctrl, data->ctrl_reg + ctrl_reg + reg_off); in loongson2_set_ctrl_regs()
79 val = readl(data->ctrl_reg + LOONGSON2_THSENS_OUT_REG); in loongson2_2k1000_get_temp()
101 writeb(LOONGSON2_THSENS_INT_EN, data->ctrl_reg + LOONGSON2_THSENS_STATUS_REG); in loongson2_thermal_irq_thread()
133 data->ctrl_reg = devm_platform_ioremap_resource(pdev, 0); in loongson2_thermal_probe()
134 if (IS_ERR(data->ctrl_reg)) in loongson2_thermal_probe()
135 return PTR_ERR(data->ctrl_reg); in loongson2_thermal_probe()
150 writeb(LOONGSON2_THSENS_INT_EN, data->ctrl_reg + LOONGSON2_THSENS_STATUS_REG); in loongson2_thermal_probe()
/linux/drivers/pci/hotplug/
H A Dcpqphp.h108 struct ctrl_reg { /* offset */ struct
140 SLOT_RST = offsetof(struct ctrl_reg, slot_RST), argument
141 SLOT_ENABLE = offsetof(struct ctrl_reg, slot_enable),
142 MISC = offsetof(struct ctrl_reg, misc),
143 LED_CONTROL = offsetof(struct ctrl_reg, led_control),
144 INT_INPUT_CLEAR = offsetof(struct ctrl_reg, int_input_clear),
145 INT_MASK = offsetof(struct ctrl_reg, int_mask),
146 CTRL_RESERVED0 = offsetof(struct ctrl_reg, reserved0),
147 CTRL_RESERVED1 = offsetof(struct ctrl_reg, reserved1),
148 CTRL_RESERVED2 = offsetof(struct ctrl_reg, reserved1),
[all …]
H A Dshpchp.h175 struct ctrl_reg { struct
193 BASE_OFFSET = offsetof(struct ctrl_reg, base_offset), argument
194 SLOT_AVAIL1 = offsetof(struct ctrl_reg, slot_avail1),
195 SLOT_AVAIL2 = offsetof(struct ctrl_reg, slot_avail2),
196 SLOT_CONFIG = offsetof(struct ctrl_reg, slot_config),
197 SEC_BUS_CONFIG = offsetof(struct ctrl_reg, sec_bus_config),
198 MSI_CTRL = offsetof(struct ctrl_reg, msi_ctrl),
199 PROG_INTERFACE = offsetof(struct ctrl_reg, prog_interface),
200 CMD = offsetof(struct ctrl_reg, cmd),
201 CMD_STATUS = offsetof(struct ctrl_reg, cmd_status),
[all …]
/linux/drivers/ntb/hw/epf/
H A Dntb_hw_epf.c75 void __iomem *ctrl_reg; member
108 writel(argument, ndev->ctrl_reg + NTB_EPF_ARGUMENT); in ntb_epf_send_command()
109 writel(command, ndev->ctrl_reg + NTB_EPF_COMMAND); in ntb_epf_send_command()
114 status = readw(ndev->ctrl_reg + NTB_EPF_CMD_STATUS); in ntb_epf_send_command()
132 writew(0, ndev->ctrl_reg + NTB_EPF_CMD_STATUS); in ntb_epf_send_command()
200 status = readw(ndev->ctrl_reg + NTB_EPF_LINK_STATUS); in ntb_epf_link_is_up()
216 offset = readl(ndev->ctrl_reg + NTB_EPF_SPAD_OFFSET); in ntb_epf_spad_read()
219 return readl(ndev->ctrl_reg + offset); in ntb_epf_spad_read()
234 offset = readl(ndev->ctrl_reg + NTB_EPF_SPAD_OFFSET); in ntb_epf_spad_write()
236 writel(val, ndev->ctrl_reg + offset); in ntb_epf_spad_write()
[all …]
/linux/drivers/net/wireless/st/cw1200/
H A Dbh.c173 u16 *ctrl_reg) in cw1200_bh_read_ctrl_reg() argument
178 ST90TDS_CONTROL_REG_ID, ctrl_reg); in cw1200_bh_read_ctrl_reg()
181 ST90TDS_CONTROL_REG_ID, ctrl_reg); in cw1200_bh_read_ctrl_reg()
191 u16 ctrl_reg; in cw1200_device_wakeup() local
208 ret = cw1200_bh_read_ctrl_reg(priv, &ctrl_reg); in cw1200_device_wakeup()
215 if (ctrl_reg & ST90TDS_CONT_RDY_BIT) { in cw1200_device_wakeup()
233 uint16_t *ctrl_reg, in cw1200_bh_rx_helper() argument
247 read_len = (*ctrl_reg & ST90TDS_CONT_NEXT_LEN_MASK) * 2; in cw1200_bh_rx_helper()
254 read_len, *ctrl_reg); in cw1200_bh_rx_helper()
288 *ctrl_reg = __le16_to_cpu( in cw1200_bh_rx_helper()
[all …]
/linux/drivers/clk/hisilicon/
H A Dclk-hix5hd2.c136 u32 ctrl_reg; member
148 void __iomem *ctrl_reg; member
174 val = readl_relaxed(clk->ctrl_reg); in clk_ether_prepare()
176 writel_relaxed(val, clk->ctrl_reg); in clk_ether_prepare()
178 writel_relaxed(val, clk->ctrl_reg); in clk_ether_prepare()
203 val = readl_relaxed(clk->ctrl_reg); in clk_ether_unprepare()
205 writel_relaxed(val, clk->ctrl_reg); in clk_ether_unprepare()
218 val = readl_relaxed(clk->ctrl_reg); in clk_complex_enable()
221 writel_relaxed(val, clk->ctrl_reg); in clk_complex_enable()
236 val = readl_relaxed(clk->ctrl_reg); in clk_complex_disable()
[all …]
/linux/drivers/phy/marvell/
H A Dphy-berlin-sata.c66 static inline void phy_berlin_sata_reg_setbits(void __iomem *ctrl_reg, in phy_berlin_sata_reg_setbits() argument
72 writel(phy_base + reg, ctrl_reg + PORT_VSR_ADDR); in phy_berlin_sata_reg_setbits()
75 regval = readl(ctrl_reg + PORT_VSR_DATA); in phy_berlin_sata_reg_setbits()
78 writel(regval, ctrl_reg + PORT_VSR_DATA); in phy_berlin_sata_reg_setbits()
85 void __iomem *ctrl_reg = priv->base + 0x60 + (desc->index * 0x80); in phy_berlin_sata_power_on() local
105 phy_berlin_sata_reg_setbits(ctrl_reg, priv->phy_base, 0x01, in phy_berlin_sata_power_on()
110 phy_berlin_sata_reg_setbits(ctrl_reg, priv->phy_base, 0x25, in phy_berlin_sata_power_on()
114 phy_berlin_sata_reg_setbits(ctrl_reg, priv->phy_base, 0x23, in phy_berlin_sata_power_on()
118 phy_berlin_sata_reg_setbits(ctrl_reg, priv->phy_base, 0x02, in phy_berlin_sata_power_on()
122 regval = readl(ctrl_reg + PORT_SCR_CTL); in phy_berlin_sata_power_on()
[all …]
/linux/drivers/spi/
H A Dspi-jcore.c44 static int jcore_spi_wait(void __iomem *ctrl_reg) in jcore_spi_wait() argument
49 if (!(readl(ctrl_reg) & JCORE_SPI_STAT_BUSY)) in jcore_spi_wait()
59 void __iomem *ctrl_reg = hw->base + CTRL_REG; in jcore_spi_program() local
61 if (jcore_spi_wait(ctrl_reg)) in jcore_spi_program()
65 writel(hw->cs_reg | hw->speed_reg, ctrl_reg); in jcore_spi_program()
102 void __iomem *ctrl_reg = hw->base + CTRL_REG; in jcore_spi_txrx() local
120 if (jcore_spi_wait(ctrl_reg)) in jcore_spi_txrx()
124 writel(xmit, ctrl_reg); in jcore_spi_txrx()
126 if (jcore_spi_wait(ctrl_reg)) in jcore_spi_txrx()
/linux/drivers/clocksource/
H A Dtimer-cadence-ttc.c113 u32 ctrl_reg; in ttc_set_interval() local
116 ctrl_reg = readl_relaxed(timer->base_addr + TTC_CNT_CNTRL_OFFSET); in ttc_set_interval()
117 ctrl_reg |= TTC_CNT_CNTRL_DISABLE_MASK; in ttc_set_interval()
118 writel_relaxed(ctrl_reg, timer->base_addr + TTC_CNT_CNTRL_OFFSET); in ttc_set_interval()
126 ctrl_reg |= CNT_CNTRL_RESET; in ttc_set_interval()
127 ctrl_reg &= ~TTC_CNT_CNTRL_DISABLE_MASK; in ttc_set_interval()
128 writel_relaxed(ctrl_reg, timer->base_addr + TTC_CNT_CNTRL_OFFSET); in ttc_set_interval()
201 u32 ctrl_reg; in ttc_shutdown() local
203 ctrl_reg = readl_relaxed(timer->base_addr + TTC_CNT_CNTRL_OFFSET); in ttc_shutdown()
204 ctrl_reg |= TTC_CNT_CNTRL_DISABLE_MASK; in ttc_shutdown()
[all …]
/linux/drivers/net/wireless/silabs/wfx/
H A Dbh.c137 int ctrl_reg, piggyback; in bh_work_rx() local
142 ctrl_reg = piggyback; in bh_work_rx()
144 ctrl_reg = atomic_xchg(&wdev->hif.ctrl_reg, 0); in bh_work_rx()
146 ctrl_reg = 0; in bh_work_rx()
147 if (!(ctrl_reg & CTRL_NEXT_LEN_MASK)) in bh_work_rx()
150 len = (ctrl_reg & CTRL_NEXT_LEN_MASK) * 2; in bh_work_rx()
159 ctrl_reg = atomic_xchg(&wdev->hif.ctrl_reg, piggyback); in bh_work_rx()
161 if (ctrl_reg) in bh_work_rx()
163 ctrl_reg, piggyback); in bh_work_rx()
268 prev = atomic_xchg(&wdev->hif.ctrl_reg, cur); in wfx_bh_request_rx()
/linux/drivers/misc/ibmasm/
H A Dlowlevel.h53 void __iomem *ctrl_reg = base_address + INTR_CONTROL_REGISTER; in ibmasm_enable_interrupts() local
54 writel( readl(ctrl_reg) & ~mask, ctrl_reg); in ibmasm_enable_interrupts()
59 void __iomem *ctrl_reg = base_address + INTR_CONTROL_REGISTER; in ibmasm_disable_interrupts() local
60 writel( readl(ctrl_reg) | mask, ctrl_reg); in ibmasm_disable_interrupts()
/linux/drivers/input/rmi4/
H A Drmi_f30.c275 u8 *ctrl_reg = f30->ctrl_regs; in rmi_f30_initialize() local
300 f30->register_count, &ctrl_reg); in rmi_f30_initialize()
303 sizeof(u8), &ctrl_reg); in rmi_f30_initialize()
307 f30->register_count, &ctrl_reg); in rmi_f30_initialize()
310 f30->register_count, &ctrl_reg); in rmi_f30_initialize()
315 f30->register_count, &ctrl_reg); in rmi_f30_initialize()
319 &ctrl_reg); in rmi_f30_initialize()
325 f30->gpioled_count, &ctrl_reg); in rmi_f30_initialize()
331 f30->gpioled_count, &ctrl_reg); in rmi_f30_initialize()
336 f30->register_count, &ctrl_reg); in rmi_f30_initialize()
[all …]
/linux/drivers/fpga/
H A Dsocfpga.c338 u32 ctrl_reg; in socfpga_fpga_cfg_mode_set() local
347 ctrl_reg = socfpga_fpga_readl(priv, SOCFPGA_FPGMGR_CTL_OFST); in socfpga_fpga_cfg_mode_set()
348 ctrl_reg &= ~SOCFPGA_FPGMGR_CTL_CDRATIO_MASK; in socfpga_fpga_cfg_mode_set()
349 ctrl_reg &= ~SOCFPGA_FPGMGR_CTL_CFGWDTH_MASK; in socfpga_fpga_cfg_mode_set()
350 ctrl_reg |= cfgmgr_modes[mode].ctrl; in socfpga_fpga_cfg_mode_set()
353 ctrl_reg &= ~SOCFPGA_FPGMGR_CTL_NCE; in socfpga_fpga_cfg_mode_set()
354 socfpga_fpga_writel(priv, SOCFPGA_FPGMGR_CTL_OFST, ctrl_reg); in socfpga_fpga_cfg_mode_set()
362 u32 ctrl_reg, status; in socfpga_fpga_reset() local
379 ctrl_reg = socfpga_fpga_readl(priv, SOCFPGA_FPGMGR_CTL_OFST); in socfpga_fpga_reset()
380 ctrl_reg |= SOCFPGA_FPGMGR_CTL_NCFGPULL; in socfpga_fpga_reset()
[all …]
/linux/drivers/tty/serial/
H A Dxilinx_uartps.c608 u32 ctrl_reg; in cdns_uart_clk_notifier_cb() local
638 ctrl_reg = readl(port->membase + CDNS_UART_CR); in cdns_uart_clk_notifier_cb()
639 ctrl_reg |= CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS; in cdns_uart_clk_notifier_cb()
640 writel(ctrl_reg, port->membase + CDNS_UART_CR); in cdns_uart_clk_notifier_cb()
665 ctrl_reg = readl(port->membase + CDNS_UART_CR); in cdns_uart_clk_notifier_cb()
666 ctrl_reg |= CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST; in cdns_uart_clk_notifier_cb()
667 writel(ctrl_reg, port->membase + CDNS_UART_CR); in cdns_uart_clk_notifier_cb()
679 ctrl_reg = readl(port->membase + CDNS_UART_CR); in cdns_uart_clk_notifier_cb()
680 ctrl_reg &= ~(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS); in cdns_uart_clk_notifier_cb()
681 ctrl_reg |= CDNS_UART_CR_TX_EN | CDNS_UART_CR_RX_EN; in cdns_uart_clk_notifier_cb()
[all …]
/linux/drivers/regulator/
H A Dvctrl-regulator.c323 struct regulator *ctrl_reg) in vctrl_init_vtable() argument
332 n_voltages = regulator_count_voltages(ctrl_reg); in vctrl_init_vtable()
338 ctrl_uV = regulator_list_voltage(ctrl_reg, i); in vctrl_init_vtable()
358 ctrl_uV = regulator_list_voltage(ctrl_reg, i); in vctrl_init_vtable()
450 struct regulator *ctrl_reg; in vctrl_probe() local
465 ctrl_reg = devm_regulator_get(&pdev->dev, "ctrl"); in vctrl_probe()
466 if (IS_ERR(ctrl_reg)) in vctrl_probe()
467 return PTR_ERR(ctrl_reg); in vctrl_probe()
477 if ((regulator_get_linear_step(ctrl_reg) == 1) || in vctrl_probe()
478 (regulator_count_voltages(ctrl_reg) == -EINVAL)) { in vctrl_probe()
[all …]
/linux/drivers/media/platform/ti/davinci/
H A Dvpif.h391 u32 ctrl_reg; in disable_raw_feature() local
393 ctrl_reg = VPIF_CH0_CTRL; in disable_raw_feature()
395 ctrl_reg = VPIF_CH1_CTRL; in disable_raw_feature()
398 vpif_clr_bit(ctrl_reg, VPIF_CH_VANC_EN_BIT); in disable_raw_feature()
400 vpif_clr_bit(ctrl_reg, VPIF_CH_HANC_EN_BIT); in disable_raw_feature()
405 u32 ctrl_reg; in enable_raw_feature() local
407 ctrl_reg = VPIF_CH0_CTRL; in enable_raw_feature()
409 ctrl_reg = VPIF_CH1_CTRL; in enable_raw_feature()
412 vpif_set_bit(ctrl_reg, VPIF_CH_VANC_EN_BIT); in enable_raw_feature()
414 vpif_set_bit(ctrl_reg, VPIF_CH_HANC_EN_BIT); in enable_raw_feature()
/linux/drivers/hwmon/
H A Daspeed-pwm-tacho.c210 u32 ctrl_reg; member
221 .ctrl_reg = ASPEED_PTCR_TYPEM_CTRL,
230 .ctrl_reg = ASPEED_PTCR_TYPEN_CTRL,
239 .ctrl_reg = ASPEED_PTCR_TYPEO_CTRL,
248 u32 ctrl_reg; member
261 .ctrl_reg = ASPEED_PTCR_CTRL,
272 .ctrl_reg = ASPEED_PTCR_CTRL,
283 .ctrl_reg = ASPEED_PTCR_CTRL,
294 .ctrl_reg = ASPEED_PTCR_CTRL,
305 .ctrl_reg = ASPEED_PTCR_CTRL_EXT,
[all …]
/linux/drivers/rtc/
H A Drtc-rk808.c45 unsigned int ctrl_reg; member
103 ret = regmap_update_bits(rk808_rtc->regmap, rk808_rtc->creg->ctrl_reg, in rk808_rtc_readtime()
117 ret = regmap_update_bits(rk808_rtc->regmap, rk808_rtc->creg->ctrl_reg, in rk808_rtc_readtime()
163 ret = regmap_update_bits(rk808_rtc->regmap, rk808_rtc->creg->ctrl_reg, in rk808_rtc_set_time()
178 ret = regmap_update_bits(rk808_rtc->regmap, rk808_rtc->creg->ctrl_reg, in rk808_rtc_set_time()
363 .ctrl_reg = RK808_RTC_CTRL_REG,
371 .ctrl_reg = RK817_RTC_CTRL_REG,
403 ret = regmap_update_bits(rk808_rtc->regmap, rk808_rtc->creg->ctrl_reg, in rk808_rtc_probe()
/linux/drivers/mmc/host/
H A Dmvsdio.c602 u32 ctrl_reg = 0; in mvsd_set_ios() local
624 ctrl_reg |= MVSD_HOST_CTRL_BIG_ENDIAN; in mvsd_set_ios()
625 ctrl_reg &= ~MVSD_HOST_CTRL_LSB_FIRST; in mvsd_set_ios()
628 ctrl_reg |= MVSD_HOST_CTRL_TMOUT_MASK; in mvsd_set_ios()
629 ctrl_reg |= MVSD_HOST_CTRL_TMOUT_EN; in mvsd_set_ios()
632 ctrl_reg |= MVSD_HOST_CTRL_PUSH_PULL_EN; in mvsd_set_ios()
635 ctrl_reg |= MVSD_HOST_CTRL_DATA_WIDTH_4_BITS; in mvsd_set_ios()
647 ctrl_reg |= MVSD_HOST_CTRL_HI_SPEED_EN; in mvsd_set_ios()
650 host->ctrl = ctrl_reg; in mvsd_set_ios()
651 mvsd_write(MVSD_HOST_CTRL, ctrl_reg); in mvsd_set_ios()
[all …]
/linux/drivers/net/wireless/realtek/rtw88/
H A Dsec.c127 u16 ctrl_reg; in rtw_sec_enable_sec_engine() local
133 ctrl_reg = rtw_read16(rtwdev, REG_CR); in rtw_sec_enable_sec_engine()
134 ctrl_reg |= RTW_SEC_ENGINE_EN; in rtw_sec_enable_sec_engine()
135 rtw_write16(rtwdev, REG_CR, ctrl_reg); in rtw_sec_enable_sec_engine()

123