Searched refs:ctrl_offset (Results 1 – 4 of 4) sorted by relevance
/linux/drivers/reset/ |
H A D | reset-lpc18xx.c | 71 u32 ctrl_offset = LPC18XX_RGU_CTRL0; in lpc18xx_rgu_setclear_reset() local 76 ctrl_offset += (id / LPC18XX_RGU_RESETS_PER_REG) * sizeof(u32); in lpc18xx_rgu_setclear_reset() 82 writel(stat | rst_bit, rc->base + ctrl_offset); in lpc18xx_rgu_setclear_reset() 84 writel(stat & ~rst_bit, rc->base + ctrl_offset); in lpc18xx_rgu_setclear_reset()
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H A D | reset-npcm.c | 122 unsigned int ctrl_offset = id >> 8; in npcm_rc_setclear_reset() local 127 stat = readl(rc->base + ctrl_offset); in npcm_rc_setclear_reset() 129 writel(stat | rst_bit, rc->base + ctrl_offset); in npcm_rc_setclear_reset() 131 writel(stat & ~rst_bit, rc->base + ctrl_offset); in npcm_rc_setclear_reset() 153 unsigned int ctrl_offset = id >> 8; in npcm_rc_status() local 155 return (readl(rc->base + ctrl_offset) & rst_bit); in npcm_rc_status()
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/linux/drivers/pinctrl/mediatek/ |
H A D | mtk-eint.c | 323 unsigned int rst, ctrl_offset; in mtk_eint_debounce_process() local 326 ctrl_offset = (index / 4) * 4 + eint->regs->dbnc_ctrl; in mtk_eint_debounce_process() 327 dbnc = readl(eint->base + ctrl_offset); in mtk_eint_debounce_process() 330 ctrl_offset = (index / 4) * 4 + eint->regs->dbnc_set; in mtk_eint_debounce_process() 332 writel(rst, eint->base + ctrl_offset); in mtk_eint_debounce_process()
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/linux/sound/soc/codecs/ |
H A D | nau8825.c | 1430 unsigned int ctrl_val = 0, ctrl_offset = 0, value = 0, dac_s, adc_s; in nau8825_set_tdm_slot() local 1460 ctrl_offset = 4 * slot_width; in nau8825_set_tdm_slot() 1462 ctrl_offset += 1; in nau8825_set_tdm_slot() 1505 NAU8825_TSLOT_L0_MASK, ctrl_offset); in nau8825_set_tdm_slot()
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