Searched refs:ctrl_bit (Results 1 – 3 of 3) sorted by relevance
| /linux/drivers/net/ethernet/hisilicon/hns3/hns3pf/ |
| H A D | hclge_mdio.c | 32 u8 ctrl_bit; member
62 hnae3_set_bit(mdio_cmd->ctrl_bit, HCLGE_MDIO_CTRL_START_B, 1); in hclge_mdio_write()
63 hnae3_set_field(mdio_cmd->ctrl_bit, HCLGE_MDIO_CTRL_ST_M, in hclge_mdio_write()
65 hnae3_set_field(mdio_cmd->ctrl_bit, HCLGE_MDIO_CTRL_OP_M, in hclge_mdio_write()
100 hnae3_set_bit(mdio_cmd->ctrl_bit, HCLGE_MDIO_CTRL_START_B, 1); in hclge_mdio_read()
101 hnae3_set_field(mdio_cmd->ctrl_bit, HCLGE_MDIO_CTRL_ST_M, in hclge_mdio_read()
103 hnae3_set_field(mdio_cmd->ctrl_bit, HCLGE_MDIO_CTRL_OP_M, in hclge_mdio_read()
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| /linux/drivers/gpu/drm/omapdrm/dss/ |
| H A D | dss.c | 477 u8 ctrl_bit = ctrl_bits[channel]; in dss_lcd_clk_mux_dra7() local
482 REG_FLD_MOD(dss, DSS_CONTROL, 0, ctrl_bit, ctrl_bit); in dss_lcd_clk_mux_dra7()
490 REG_FLD_MOD(dss, DSS_CONTROL, 1, ctrl_bit, ctrl_bit); in dss_lcd_clk_mux_dra7()
510 u8 ctrl_bit = ctrl_bits[channel]; in dss_lcd_clk_mux_omap5() local
514 REG_FLD_MOD(dss, DSS_CONTROL, 0, ctrl_bit, ctrl_bit); in dss_lcd_clk_mux_omap5()
521 REG_FLD_MOD(dss, DSS_CONTROL, 1, ctrl_bit, ctrl_bit); in dss_lcd_clk_mux_omap5()
539 u8 ctrl_bit = ctrl_bits[channel]; in dss_lcd_clk_mux_omap4() local
543 REG_FLD_MOD(dss, DSS_CONTROL, 0, ctrl_bit, ctrl_bit); in dss_lcd_clk_mux_omap4()
550 REG_FLD_MOD(dss, DSS_CONTROL, 1, ctrl_bit, ctrl_bit); in dss_lcd_clk_mux_omap4()
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| /linux/drivers/net/ethernet/netronome/nfp/nfpcore/ |
| H A D | nfp_nsp_eth.c | 513 u64 val, const u64 ctrl_bit) in nfp_eth_set_bit_config() argument
537 entries[idx].control |= cpu_to_le64(ctrl_bit); in nfp_eth_set_bit_config()
574 #define NFP_ETH_SET_BIT_CONFIG(nsp, raw_idx, mask, val, ctrl_bit) \ argument
578 val, ctrl_bit); \
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