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Searched refs:ctrl (Results 1 – 25 of 1364) sorted by relevance

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/linux/drivers/pci/hotplug/
H A Dpciehp_ctrl.c33 static void set_slot_off(struct controller *ctrl) in set_slot_off() argument
39 if (POWER_CTRL(ctrl)) { in set_slot_off()
40 pciehp_power_off_slot(ctrl); in set_slot_off()
50 pciehp_set_indicators(ctrl, PCI_EXP_SLTCTL_PWR_IND_OFF, in set_slot_off()
61 static int board_added(struct controller *ctrl) in board_added() argument
64 struct pci_bus *parent = ctrl->pcie->port->subordinate; in board_added()
66 if (POWER_CTRL(ctrl)) { in board_added()
68 retval = pciehp_power_on_slot(ctrl); in board_added()
73 pciehp_set_indicators(ctrl, PCI_EXP_SLTCTL_PWR_IND_BLINK, in board_added()
77 retval = pciehp_check_link_status(ctrl); in board_added()
[all …]
H A Dpciehp_hpc.c49 static inline struct pci_dev *ctrl_dev(struct controller *ctrl) in ctrl_dev() argument
51 return ctrl->pcie->port; in ctrl_dev()
58 static inline int pciehp_request_irq(struct controller *ctrl) in pciehp_request_irq() argument
60 int retval, irq = ctrl->pcie->irq; in pciehp_request_irq()
63 ctrl->poll_thread = kthread_run(&pciehp_poll, ctrl, in pciehp_request_irq()
65 slot_name(ctrl)); in pciehp_request_irq()
66 return PTR_ERR_OR_ZERO(ctrl->poll_thread); in pciehp_request_irq()
71 IRQF_SHARED, "pciehp", ctrl); in pciehp_request_irq()
73 ctrl_err(ctrl, "Cannot get irq %d for the hotplug controller\n", in pciehp_request_irq()
78 static inline void pciehp_free_irq(struct controller *ctrl) in pciehp_free_irq() argument
[all …]
H A Dshpchp_hpc.c169 static void start_int_poll_timer(struct controller *ctrl, int sec);
171 static inline u8 shpc_readb(struct controller *ctrl, int reg) in shpc_readb() argument
173 return readb(ctrl->creg + reg); in shpc_readb()
176 static inline u16 shpc_readw(struct controller *ctrl, int reg) in shpc_readw() argument
178 return readw(ctrl->creg + reg); in shpc_readw()
181 static inline void shpc_writew(struct controller *ctrl, int reg, u16 val) in shpc_writew() argument
183 writew(val, ctrl->creg + reg); in shpc_writew()
186 static inline u32 shpc_readl(struct controller *ctrl, int reg) in shpc_readl() argument
188 return readl(ctrl->creg + reg); in shpc_readl()
191 static inline void shpc_writel(struct controller *ctrl, int reg, u32 val) in shpc_writel() argument
[all …]
H A Dcpqphp_core.c120 static int init_SERR(struct controller *ctrl) in init_SERR() argument
125 if (!ctrl) in init_SERR()
128 tempdword = ctrl->first_slot; in init_SERR()
130 number_of_slots = readb(ctrl->hpc_reg + SLOT_MASK) & 0x0F; in init_SERR()
133 writeb(0, ctrl->hpc_reg + SLOT_SERR); in init_SERR()
266 static int ctrl_slot_cleanup(struct controller *ctrl) in ctrl_slot_cleanup() argument
270 old_slot = ctrl->slot; in ctrl_slot_cleanup()
271 ctrl->slot = NULL; in ctrl_slot_cleanup()
280 cpqhp_remove_debugfs_files(ctrl); in ctrl_slot_cleanup()
283 free_irq(ctrl->interrupt, ctrl); in ctrl_slot_cleanup()
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H A Dpciehp_core.c51 static int init_slot(struct controller *ctrl) in init_slot() argument
67 if (MRL_SENS(ctrl)) in init_slot()
69 if (ATTN_LED(ctrl)) { in init_slot()
72 } else if (ctrl->pcie->port->hotplug_user_indicators) { in init_slot()
78 ctrl->hotplug_slot.ops = ops; in init_slot()
79 snprintf(name, SLOT_NAME_SIZE, "%u", PSN(ctrl)); in init_slot()
81 retval = pci_hp_initialize(&ctrl->hotplug_slot, in init_slot()
82 ctrl->pcie->port->subordinate, 0, name); in init_slot()
84 ctrl_err(ctrl, "pci_hp_initialize failed: error %d\n", retval); in init_slot()
90 static void cleanup_slot(struct controller *ctrl) in cleanup_slot() argument
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H A Dpciehp.h35 #define ctrl_dbg(ctrl, format, arg...) \ argument
36 pci_dbg(ctrl->pcie->port, format, ## arg)
37 #define ctrl_err(ctrl, format, arg...) \ argument
38 pci_err(ctrl->pcie->port, format, ## arg)
39 #define ctrl_info(ctrl, format, arg...) \ argument
40 pci_info(ctrl->pcie->port, format, ## arg)
41 #define ctrl_warn(ctrl, format, arg...) \ argument
42 pci_warn(ctrl->pcie->port, format, ## arg)
156 #define ATTN_BUTTN(ctrl) ((ctrl)->slot_cap & PCI_EXP_SLTCAP_ABP) argument
157 #define POWER_CTRL(ctrl) ((ctrl)->slot_cap & PCI_EXP_SLTCAP_PCP) argument
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H A Dshpchp_ctrl.c45 u8 shpchp_handle_attention_button(u8 hp_slot, struct controller *ctrl) in shpchp_handle_attention_button() argument
51 ctrl_dbg(ctrl, "Attention button interrupt received\n"); in shpchp_handle_attention_button()
53 p_slot = shpchp_find_slot(ctrl, hp_slot + ctrl->slot_device_offset); in shpchp_handle_attention_button()
59 ctrl_info(ctrl, "Button pressed on Slot(%s)\n", slot_name(p_slot)); in shpchp_handle_attention_button()
68 u8 shpchp_handle_switch_change(u8 hp_slot, struct controller *ctrl) in shpchp_handle_switch_change() argument
75 ctrl_dbg(ctrl, "Switch interrupt received\n"); in shpchp_handle_switch_change()
77 p_slot = shpchp_find_slot(ctrl, hp_slot + ctrl->slot_device_offset); in shpchp_handle_switch_change()
80 ctrl_dbg(ctrl, "Card present %x Power status %x\n", in shpchp_handle_switch_change()
87 ctrl_info(ctrl, "Latch open on Slot(%s)\n", slot_name(p_slot)); in shpchp_handle_switch_change()
91 ctrl_err(ctrl, "Surprise Removal of card\n"); in shpchp_handle_switch_change()
[all …]
H A Dcpqphp_ctrl.c28 static u32 configure_new_device(struct controller *ctrl, struct pci_func *func,
30 static int configure_new_function(struct controller *ctrl, struct pci_func *func,
32 static void interrupt_event_handler(struct controller *ctrl);
53 static u8 handle_switch_change(u8 change, struct controller *ctrl) in handle_switch_change() argument
72 func = cpqhp_slot_find(ctrl->bus, in handle_switch_change()
73 (hp_slot + ctrl->slot_device_offset), 0); in handle_switch_change()
78 taskInfo = &(ctrl->event_queue[ctrl->next_event]); in handle_switch_change()
79 ctrl->next_event = (ctrl->next_event + 1) % 10; in handle_switch_change()
84 temp_word = ctrl->ctrl_int_comp >> 16; in handle_switch_change()
88 if (ctrl->ctrl_int_comp & (0x1L << hp_slot)) { in handle_switch_change()
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/linux/drivers/soundwire/
H A Dqcom.c220 int (*reg_read)(struct qcom_swrm_ctrl *ctrl, int reg, u32 *val);
221 int (*reg_write)(struct qcom_swrm_ctrl *ctrl, int reg, int val);
331 static int qcom_swrm_ahb_reg_read(struct qcom_swrm_ctrl *ctrl, int reg, in qcom_swrm_ahb_reg_read() argument
334 struct regmap *wcd_regmap = ctrl->regmap; in qcom_swrm_ahb_reg_read()
351 static int qcom_swrm_ahb_reg_write(struct qcom_swrm_ctrl *ctrl, in qcom_swrm_ahb_reg_write() argument
354 struct regmap *wcd_regmap = ctrl->regmap; in qcom_swrm_ahb_reg_write()
371 static int qcom_swrm_cpu_reg_read(struct qcom_swrm_ctrl *ctrl, int reg, in qcom_swrm_cpu_reg_read() argument
374 *val = readl(ctrl->mmio + reg); in qcom_swrm_cpu_reg_read()
378 static int qcom_swrm_cpu_reg_write(struct qcom_swrm_ctrl *ctrl, int reg, in qcom_swrm_cpu_reg_write() argument
381 writel(val, ctrl->mmio + reg); in qcom_swrm_cpu_reg_write()
[all …]
/linux/drivers/gpu/drm/msm/dp/
H A Ddp_ctrl.c145 static inline u32 msm_dp_read_ahb(const struct msm_dp_ctrl_private *ctrl, u32 offset) in msm_dp_read_ahb() argument
147 return readl_relaxed(ctrl->ahb_base + offset); in msm_dp_read_ahb()
150 static inline void msm_dp_write_ahb(struct msm_dp_ctrl_private *ctrl, in msm_dp_write_ahb() argument
157 writel(data, ctrl->ahb_base + offset); in msm_dp_write_ahb()
160 static inline u32 msm_dp_read_link(struct msm_dp_ctrl_private *ctrl, u32 offset) in msm_dp_read_link() argument
162 return readl_relaxed(ctrl->link_base + offset); in msm_dp_read_link()
165 static inline void msm_dp_write_link(struct msm_dp_ctrl_private *ctrl, in msm_dp_write_link() argument
172 writel(data, ctrl->link_base + offset); in msm_dp_write_link()
199 struct msm_dp_ctrl_private *ctrl = in msm_dp_ctrl_reset() local
203 sw_reset = msm_dp_read_ahb(ctrl, REG_DP_SW_RESET); in msm_dp_ctrl_reset()
[all …]
/linux/drivers/nvme/host/
H A Dfc.c35 struct nvme_fc_ctrl *ctrl; member
99 struct nvme_fc_ctrl *ctrl; member
179 struct nvme_ctrl ctrl; member
183 to_fc_ctrl(struct nvme_ctrl *ctrl) in to_fc_ctrl() argument
185 return container_of(ctrl, struct nvme_fc_ctrl, ctrl); in to_fc_ctrl()
552 nvme_fc_resume_controller(struct nvme_fc_ctrl *ctrl) in nvme_fc_resume_controller() argument
554 switch (nvme_ctrl_state(&ctrl->ctrl)) { in nvme_fc_resume_controller()
561 dev_info(ctrl->ctrl.device, in nvme_fc_resume_controller()
563 "Attempting reconnect\n", ctrl->cnum); in nvme_fc_resume_controller()
565 queue_delayed_work(nvme_wq, &ctrl->connect_work, 0); in nvme_fc_resume_controller()
[all …]
H A Dauth.c24 struct nvme_ctrl *ctrl; member
54 static inline int ctrl_max_dhchaps(struct nvme_ctrl *ctrl) in ctrl_max_dhchaps() argument
56 return ctrl->opts->nr_io_queues + ctrl->opts->nr_write_queues + in ctrl_max_dhchaps()
57 ctrl->opts->nr_poll_queues + 1; in ctrl_max_dhchaps()
60 static int nvme_auth_submit(struct nvme_ctrl *ctrl, int qid, in nvme_auth_submit() argument
65 struct request_queue *q = ctrl->fabrics_q; in nvme_auth_submit()
70 q = ctrl->connect_q; in nvme_auth_submit()
88 dev_warn(ctrl->device, in nvme_auth_submit()
91 dev_err(ctrl->device, in nvme_auth_submit()
96 static int nvme_auth_receive_validate(struct nvme_ctrl *ctrl, int qid, in nvme_auth_receive_validate() argument
[all …]
H A Dtcp.c164 struct nvme_tcp_ctrl *ctrl; member
194 struct nvme_ctrl ctrl; member
209 static inline struct nvme_tcp_ctrl *to_tcp_ctrl(struct nvme_ctrl *ctrl) in to_tcp_ctrl() argument
211 return container_of(ctrl, struct nvme_tcp_ctrl, ctrl); in to_tcp_ctrl()
216 return queue - queue->ctrl->queues; in nvme_tcp_queue_id()
246 static inline bool nvme_tcp_tls_configured(struct nvme_ctrl *ctrl) in nvme_tcp_tls_configured() argument
251 return ctrl->opts->tls || ctrl->opts->concat; in nvme_tcp_tls_configured()
259 return queue->ctrl->admin_tag_set.tags[queue_idx]; in nvme_tcp_tagset()
260 return queue->ctrl->tag_set.tags[queue_idx - 1]; in nvme_tcp_tagset()
294 return req == &req->queue->ctrl->async_req; in nvme_tcp_async_req()
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/linux/drivers/net/mdio/
H A Dmdio-bitbang.c44 static void mdiobb_send_bit(struct mdiobb_ctrl *ctrl, int val) in mdiobb_send_bit() argument
46 const struct mdiobb_ops *ops = ctrl->ops; in mdiobb_send_bit()
48 ops->set_mdio_data(ctrl, val); in mdiobb_send_bit()
50 ops->set_mdc(ctrl, 1); in mdiobb_send_bit()
52 ops->set_mdc(ctrl, 0); in mdiobb_send_bit()
56 static int mdiobb_get_bit(struct mdiobb_ctrl *ctrl) in mdiobb_get_bit() argument
58 const struct mdiobb_ops *ops = ctrl->ops; in mdiobb_get_bit()
61 ops->set_mdc(ctrl, 1); in mdiobb_get_bit()
63 ops->set_mdc(ctrl, 0); in mdiobb_get_bit()
65 return ops->get_mdio_data(ctrl); in mdiobb_get_bit()
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/linux/drivers/nvme/target/
H A Dauth.c74 int nvmet_setup_dhgroup(struct nvmet_ctrl *ctrl, u8 dhgroup_id) in nvmet_setup_dhgroup() argument
80 __func__, ctrl->cntlid, dhgroup_id); in nvmet_setup_dhgroup()
82 if (ctrl->dh_tfm) { in nvmet_setup_dhgroup()
83 if (ctrl->dh_gid == dhgroup_id) { in nvmet_setup_dhgroup()
85 __func__, ctrl->cntlid, dhgroup_id); in nvmet_setup_dhgroup()
88 crypto_free_kpp(ctrl->dh_tfm); in nvmet_setup_dhgroup()
89 ctrl->dh_tfm = NULL; in nvmet_setup_dhgroup()
90 ctrl->dh_gid = 0; in nvmet_setup_dhgroup()
99 __func__, ctrl->cntlid, dhgroup_id); in nvmet_setup_dhgroup()
102 ctrl->dh_tfm = crypto_alloc_kpp(dhgroup_kpp, 0, 0); in nvmet_setup_dhgroup()
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H A Dcore.c134 static void nvmet_async_events_failall(struct nvmet_ctrl *ctrl) in nvmet_async_events_failall() argument
138 mutex_lock(&ctrl->lock); in nvmet_async_events_failall()
139 while (ctrl->nr_async_event_cmds) { in nvmet_async_events_failall()
140 req = ctrl->async_event_cmds[--ctrl->nr_async_event_cmds]; in nvmet_async_events_failall()
141 mutex_unlock(&ctrl->lock); in nvmet_async_events_failall()
143 mutex_lock(&ctrl->lock); in nvmet_async_events_failall()
145 mutex_unlock(&ctrl->lock); in nvmet_async_events_failall()
148 static void nvmet_async_events_process(struct nvmet_ctrl *ctrl) in nvmet_async_events_process() argument
153 mutex_lock(&ctrl->lock); in nvmet_async_events_process()
154 while (ctrl->nr_async_event_cmds && !list_empty(&ctrl->async_events)) { in nvmet_async_events_process()
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H A Dpci-epf.c84 struct nvmet_pci_epf_ctrl *ctrl; member
129 struct nvmet_pci_epf_ctrl *ctrl; member
209 struct nvmet_pci_epf_ctrl ctrl; member
226 static inline u32 nvmet_pci_epf_bar_read32(struct nvmet_pci_epf_ctrl *ctrl, in nvmet_pci_epf_bar_read32() argument
229 __le32 *bar_reg = ctrl->bar + off; in nvmet_pci_epf_bar_read32()
234 static inline void nvmet_pci_epf_bar_write32(struct nvmet_pci_epf_ctrl *ctrl, in nvmet_pci_epf_bar_write32() argument
237 __le32 *bar_reg = ctrl->bar + off; in nvmet_pci_epf_bar_write32()
242 static inline u64 nvmet_pci_epf_bar_read64(struct nvmet_pci_epf_ctrl *ctrl, in nvmet_pci_epf_bar_read64() argument
245 return (u64)nvmet_pci_epf_bar_read32(ctrl, off) | in nvmet_pci_epf_bar_read64()
246 ((u64)nvmet_pci_epf_bar_read32(ctrl, off + 4) << 32); in nvmet_pci_epf_bar_read64()
[all …]
/linux/drivers/watchdog/
H A Drealtek_otto_wdt.c76 struct otto_wdt_ctrl *ctrl = watchdog_get_drvdata(wdev); in otto_wdt_start() local
79 v = ioread32(ctrl->base + OTTO_WDT_REG_CTRL); in otto_wdt_start()
81 iowrite32(v, ctrl->base + OTTO_WDT_REG_CTRL); in otto_wdt_start()
88 struct otto_wdt_ctrl *ctrl = watchdog_get_drvdata(wdev); in otto_wdt_stop() local
91 v = ioread32(ctrl->base + OTTO_WDT_REG_CTRL); in otto_wdt_stop()
93 iowrite32(v, ctrl->base + OTTO_WDT_REG_CTRL); in otto_wdt_stop()
100 struct otto_wdt_ctrl *ctrl = watchdog_get_drvdata(wdev); in otto_wdt_ping() local
102 iowrite32(OTTO_WDT_CNTR_PING, ctrl->base + OTTO_WDT_REG_CNTR); in otto_wdt_ping()
107 static int otto_wdt_tick_ms(struct otto_wdt_ctrl *ctrl, int prescale) in otto_wdt_tick_ms() argument
109 return DIV_ROUND_CLOSEST(1 << (25 + prescale), ctrl->clk_rate_khz); in otto_wdt_tick_ms()
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/linux/drivers/clk/bcm/
H A Dclk-iproc-pll.c68 const struct iproc_pll_ctrl *ctrl; member
76 const struct iproc_clk_ctrl *ctrl; member
150 const struct iproc_pll_ctrl *ctrl = pll->ctrl; in pll_wait_for_lock() local
153 u32 val = readl(pll->status_base + ctrl->status.offset); in pll_wait_for_lock()
155 if (val & (1 << ctrl->status.shift)) in pll_wait_for_lock()
166 const struct iproc_pll_ctrl *ctrl = pll->ctrl; in iproc_pll_write() local
170 if (unlikely(ctrl->flags & IPROC_CLK_NEEDS_READ_BACK && in iproc_pll_write()
177 const struct iproc_pll_ctrl *ctrl = pll->ctrl; in __pll_disable() local
180 if (ctrl->flags & IPROC_CLK_PLL_ASIU) { in __pll_disable()
181 val = readl(pll->asiu_base + ctrl->asiu.offset); in __pll_disable()
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/linux/arch/arm/kernel/
H A Dunwind.c211 static unsigned long unwind_get_byte(struct unwind_ctrl_block *ctrl) in unwind_get_byte() argument
215 if (ctrl->entries <= 0) { in unwind_get_byte()
220 ret = (*ctrl->insn >> (ctrl->byte * 8)) & 0xff; in unwind_get_byte()
222 if (ctrl->byte == 0) { in unwind_get_byte()
223 ctrl->insn++; in unwind_get_byte()
224 ctrl->entries--; in unwind_get_byte()
225 ctrl->byte = 3; in unwind_get_byte()
227 ctrl->byte--; in unwind_get_byte()
233 static int unwind_pop_register(struct unwind_ctrl_block *ctrl, in unwind_pop_register() argument
236 if (unlikely(ctrl->check_each_pop)) in unwind_pop_register()
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/linux/sound/soc/codecs/
H A Dwcd-clsh-v2.c119 static inline void wcd_enable_clsh_block(struct wcd_clsh_ctrl *ctrl, in wcd_enable_clsh_block() argument
122 struct snd_soc_component *comp = ctrl->comp; in wcd_enable_clsh_block()
124 if ((enable && ++ctrl->clsh_users == 1) || in wcd_enable_clsh_block()
125 (!enable && --ctrl->clsh_users == 0)) in wcd_enable_clsh_block()
129 if (ctrl->clsh_users < 0) in wcd_enable_clsh_block()
130 ctrl->clsh_users = 0; in wcd_enable_clsh_block()
175 static void wcd_clsh_buck_ctrl(struct wcd_clsh_ctrl *ctrl, in wcd_clsh_buck_ctrl() argument
179 struct snd_soc_component *comp = ctrl->comp; in wcd_clsh_buck_ctrl()
182 if ((enable && (++ctrl->buck_users == 1)) || in wcd_clsh_buck_ctrl()
183 (!enable && (--ctrl->buck_users == 0))) in wcd_clsh_buck_ctrl()
[all …]
/linux/drivers/gpio/
H A Dgpio-en7523.c33 struct airoha_gpio_ctrl *ctrl = gpiochip_get_data(gc); in airoha_dir_set() local
34 u32 dir = ioread32(ctrl->dir[gpio / 16]); in airoha_dir_set()
35 u32 output = ioread32(ctrl->output); in airoha_dir_set()
46 iowrite32(dir, ctrl->dir[gpio / 16]); in airoha_dir_set()
49 gpio_generic_chip_set(&ctrl->gen_gc, gpio, val); in airoha_dir_set()
51 iowrite32(output, ctrl->output); in airoha_dir_set()
69 struct airoha_gpio_ctrl *ctrl = gpiochip_get_data(gc); in airoha_get_dir() local
70 u32 dir = ioread32(ctrl->dir[gpio / 16]); in airoha_get_dir()
80 struct airoha_gpio_ctrl *ctrl; in airoha_gpio_probe() local
83 ctrl = devm_kzalloc(dev, sizeof(*ctrl), GFP_KERNEL); in airoha_gpio_probe()
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/linux/drivers/mtd/nand/raw/
H A Dtegra_nand.c253 struct tegra_nand_controller *ctrl = data; in tegra_nand_irq() local
256 isr = readl_relaxed(ctrl->regs + ISR); in tegra_nand_irq()
257 dma = readl_relaxed(ctrl->regs + DMA_MST_CTRL); in tegra_nand_irq()
258 dev_dbg(ctrl->dev, "isr %08x\n", isr); in tegra_nand_irq()
269 ctrl->last_read_error = true; in tegra_nand_irq()
272 complete(&ctrl->command_complete); in tegra_nand_irq()
275 dev_err(ctrl->dev, "FIFO underrun\n"); in tegra_nand_irq()
278 dev_err(ctrl->dev, "FIFO overrun\n"); in tegra_nand_irq()
282 writel_relaxed(dma, ctrl->regs + DMA_MST_CTRL); in tegra_nand_irq()
283 complete(&ctrl->dma_complete); in tegra_nand_irq()
[all …]
/linux/drivers/platform/surface/aggregator/
H A Dcontroller.h223 #define ssam_dbg(ctrl, fmt, ...) rtl_dbg(&(ctrl)->rtl, fmt, ##__VA_ARGS__) argument
224 #define ssam_info(ctrl, fmt, ...) rtl_info(&(ctrl)->rtl, fmt, ##__VA_ARGS__) argument
225 #define ssam_warn(ctrl, fmt, ...) rtl_warn(&(ctrl)->rtl, fmt, ##__VA_ARGS__) argument
226 #define ssam_err(ctrl, fmt, ...) rtl_err(&(ctrl)->rtl, fmt, ##__VA_ARGS__) argument
241 ssize_t ssam_controller_receive_buf(struct ssam_controller *ctrl, const u8 *buf, in ssam_controller_receive_buf() argument
244 return ssh_ptl_rx_rcvbuf(&ctrl->rtl.ptl, buf, n); in ssam_controller_receive_buf()
252 static inline void ssam_controller_write_wakeup(struct ssam_controller *ctrl) in ssam_controller_write_wakeup() argument
254 ssh_ptl_tx_wakeup_transfer(&ctrl->rtl.ptl); in ssam_controller_write_wakeup()
257 int ssam_controller_init(struct ssam_controller *ctrl, struct serdev_device *s);
258 int ssam_controller_start(struct ssam_controller *ctrl);
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/linux/drivers/scsi/be2iscsi/
H A Dbe_cmds.c91 struct be_queue_info *mccq = &phba->ctrl.mcc_obj.q; in alloc_mcc_wrb()
95 spin_lock(&phba->ctrl.mcc_lock); in alloc_mcc_wrb()
100 mccq->used, phba->ctrl.mcc_tag_available); in alloc_mcc_wrb()
104 if (!phba->ctrl.mcc_tag_available) in alloc_mcc_wrb()
107 tag = phba->ctrl.mcc_tag[phba->ctrl.mcc_alloc_index]; in alloc_mcc_wrb()
112 phba->ctrl.mcc_tag_available, in alloc_mcc_wrb()
113 phba->ctrl.mcc_alloc_index); in alloc_mcc_wrb()
119 phba->ctrl.mcc_tag[phba->ctrl.mcc_alloc_index] = 0; in alloc_mcc_wrb()
120 phba->ctrl.mcc_tag_status[tag] = 0; in alloc_mcc_wrb()
121 phba->ctrl.ptag_state[tag].tag_state = 0; in alloc_mcc_wrb()
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