| /linux/drivers/clk/bcm/ |
| H A D | clk-bcm2835.c | 491 u32 ctl_reg; member 514 u32 ctl_reg; member 938 return (cprman_read(cprman, data->ctl_reg) & CM_ENABLE) != 0; in bcm2835_clock_is_on() 1053 while (cprman_read(cprman, data->ctl_reg) & CM_BUSY) { in bcm2835_clock_wait_busy() 1070 cprman_write(cprman, data->ctl_reg, in bcm2835_clock_off() 1071 cprman_read(cprman, data->ctl_reg) & ~CM_ENABLE); in bcm2835_clock_off() 1085 cprman_write(cprman, data->ctl_reg, in bcm2835_clock_on() 1086 cprman_read(cprman, data->ctl_reg) | in bcm2835_clock_on() 1124 ctl = cprman_read(cprman, data->ctl_reg) & ~CM_FRAC; in bcm2835_clock_set_rate() 1126 cprman_write(cprman, data->ctl_reg, ctl); in bcm2835_clock_set_rate() [all …]
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| /linux/drivers/net/ethernet/aquantia/atlantic/macsec/ |
| H A D | macsec_api.c | 1996 struct mss_egress_ctl_register ctl_reg; in clear_egress_counters() local 1999 memset(&ctl_reg, 0, sizeof(ctl_reg)); in clear_egress_counters() 2002 &ctl_reg.word_0); in clear_egress_counters() 2007 &ctl_reg.word_1); in clear_egress_counters() 2012 ctl_reg.bits_0.clear_counter = 0; in clear_egress_counters() 2014 MSS_EGRESS_CTL_REGISTER_ADDR, ctl_reg.word_0); in clear_egress_counters() 2019 ctl_reg.word_1); in clear_egress_counters() 2023 ctl_reg.bits_0.clear_counter = 1; in clear_egress_counters() 2025 MSS_EGRESS_CTL_REGISTER_ADDR, ctl_reg.word_0); in clear_egress_counters() 2030 ctl_reg.word_1); in clear_egress_counters() [all …]
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| /linux/drivers/scsi/csiostor/ |
| H A D | csio_mb.c | 1162 uint32_t ctl_reg = PF_REG(hw->pfn, CIM_PF_MAILBOX_CTRL_A); in csio_mb_debug_cmd_handler() local 1174 MBOWNER_V(CSIO_MBOWNER_FW), ctl_reg); in csio_mb_debug_cmd_handler() 1176 csio_rd_reg32(hw, ctl_reg); in csio_mb_debug_cmd_handler() 1196 uint32_t ctl_reg = PF_REG(hw->pfn, CIM_PF_MAILBOX_CTRL_A); in csio_mb_issue() local 1233 owner = MBOWNER_G(csio_rd_reg32(hw, ctl_reg)); in csio_mb_issue() 1238 owner = MBOWNER_G(csio_rd_reg32(hw, ctl_reg)); in csio_mb_issue() 1281 MBOWNER_V(CSIO_MBOWNER_FW), ctl_reg); in csio_mb_issue() 1284 ctl_reg); in csio_mb_issue() 1287 csio_rd_reg32(hw, ctl_reg); in csio_mb_issue() 1302 ctl = csio_rd_reg32(hw, ctl_reg); in csio_mb_issue() [all …]
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| /linux/sound/pci/echoaudio/ |
| H A D | echoaudio_3g.c | 61 __le32 ctl_reg, frq_reg; in write_control_reg() local 69 ctl_reg = cpu_to_le32(ctl); in write_control_reg() 72 if (ctl_reg != chip->comm_page->control_register || in write_control_reg() 75 chip->comm_page->control_register = ctl_reg; in write_control_reg()
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| /linux/drivers/misc/ |
| H A D | phantom.c | 60 u32 ctl_reg; member 119 r.value |= dev->ctl_reg & PHN_CTL_AMP; in phantom_ioctl() 120 dev->ctl_reg = r.value; in phantom_ioctl() 308 dev->ctl_reg ^= PHN_CTL_AMP; in phantom_isr() 309 iowrite32(dev->ctl_reg, dev->iaddr + PHN_CONTROL); in phantom_isr()
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| /linux/drivers/pinctrl/qcom/ |
| H A D | pinctrl-msm.c | 668 u32 ctl_reg, io_reg; in msm_gpio_dbg_show_one() local 687 ctl_reg = msm_readl_ctl(pctrl, g); in msm_gpio_dbg_show_one() 690 is_out = !!(ctl_reg & BIT(g->oe_bit)); in msm_gpio_dbg_show_one() 691 func = (ctl_reg >> g->mux_bit) & 7; in msm_gpio_dbg_show_one() 692 drive = (ctl_reg >> g->drv_bit) & 7; in msm_gpio_dbg_show_one() 693 pull = (ctl_reg >> g->pull_bit) & 3; in msm_gpio_dbg_show_one() 695 if (pctrl->soc->egpio_func && ctl_reg & BIT(g->egpio_present)) in msm_gpio_dbg_show_one() 696 egpio_enable = !(ctl_reg & BIT(g->egpio_enable)); in msm_gpio_dbg_show_one()
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| H A D | pinctrl-msm.h | 100 u32 ctl_reg; member
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| H A D | pinctrl-ipq8064.c | 182 .ctl_reg = 0x1000 + 0x10 * id, \ 209 .ctl_reg = ctl, \
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| H A D | pinctrl-sc8280xp.c | 30 .ctl_reg = REG_SIZE * id, \ 57 .ctl_reg = ctl, \ 81 .ctl_reg = offset, \
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| H A D | pinctrl-ipq5018.c | 30 .ctl_reg = REG_SIZE * id, \
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| H A D | pinctrl-ipq9650.c | 18 .ctl_reg = REG_SIZE * id, \
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| H A D | pinctrl-maili.c | 33 .ctl_reg = REG_SIZE * id, \ 62 .ctl_reg = ctl, \ 86 .ctl_reg = ctl, \
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| H A D | pinctrl-x1e80100.c | 32 .ctl_reg = REG_SIZE * id, \ 60 .ctl_reg = ctl, \ 84 .ctl_reg = offset, \
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| H A D | pinctrl-shikra.c | 33 .ctl_reg = REG_SIZE * id, \ 61 .ctl_reg = ctl, \
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| /linux/drivers/net/ethernet/intel/ice/ |
| H A D | ice_ptp.c | 2026 u32 ctl_reg; member 2039 .ctl_reg = GLHH_ART_CTL, 2053 .ctl_reg = E830_GLPTM_ART_CTL, 2125 ctl = rd32(hw, cfg->ctl_reg); in ice_capture_crosststamp() 2127 wr32(hw, cfg->ctl_reg, ctl); in ice_capture_crosststamp() 2130 err = rd32_poll_timeout(hw, cfg->ctl_reg, ctl, !(ctl & cfg->ctl_active), in ice_capture_crosststamp()
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| /linux/drivers/scsi/lpfc/ |
| H A D | lpfc_debugfs.c | 4935 void __iomem *ctl_reg; in lpfc_idiag_ctlacc_write() local 4971 ctl_reg = phba->sli4_hba.conf_regs_memmap_p + in lpfc_idiag_ctlacc_write() 4975 ctl_reg = phba->sli4_hba.conf_regs_memmap_p + in lpfc_idiag_ctlacc_write() 4979 ctl_reg = phba->sli4_hba.conf_regs_memmap_p + in lpfc_idiag_ctlacc_write() 4983 ctl_reg = phba->sli4_hba.conf_regs_memmap_p + in lpfc_idiag_ctlacc_write() 4987 ctl_reg = phba->sli4_hba.conf_regs_memmap_p + in lpfc_idiag_ctlacc_write() 4991 ctl_reg = phba->sli4_hba.conf_regs_memmap_p + in lpfc_idiag_ctlacc_write() 5001 reg_val = readl(ctl_reg); in lpfc_idiag_ctlacc_write() 5005 reg_val = readl(ctl_reg); in lpfc_idiag_ctlacc_write() 5008 writel(reg_val, ctl_reg); in lpfc_idiag_ctlacc_write() [all …]
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| /linux/sound/soc/ti/ |
| H A D | davinci-mcasp.c | 184 static void mcasp_set_ctl_reg(struct davinci_mcasp *mcasp, u32 ctl_reg, u32 val) in mcasp_is_synchronous() 188 mcasp_set_bits(mcasp, ctl_reg, val); in mcasp_set_clk_pdir() 193 if ((mcasp_get_reg(mcasp, ctl_reg) & val) == val) in mcasp_set_clk_pdir() 197 if (i == 1000 && ((mcasp_get_reg(mcasp, ctl_reg) & val) != val)) in mcasp_set_clk_pdir() 163 mcasp_set_ctl_reg(struct davinci_mcasp * mcasp,u32 ctl_reg,u32 val) mcasp_set_ctl_reg() argument
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| /linux/drivers/net/ethernet/chelsio/cxgb4/ |
| H A D | t4_hw.c | 298 u32 ctl_reg = PF_REG(mbox, CIM_PF_MAILBOX_CTRL_A); in t4_wr_mbox_meat_timeout() local 367 v = MBOWNER_G(t4_read_reg(adap, ctl_reg)); in t4_wr_mbox_meat_timeout() 369 v = MBOWNER_G(t4_read_reg(adap, ctl_reg)); in t4_wr_mbox_meat_timeout() 384 t4_write_reg(adap, ctl_reg, MBMSGVALID_F | MBOWNER_V(MBOX_OWNER_FW)); in t4_wr_mbox_meat_timeout() 385 t4_read_reg(adap, ctl_reg); /* flush write */ in t4_wr_mbox_meat_timeout() 402 v = t4_read_reg(adap, ctl_reg); in t4_wr_mbox_meat_timeout() 405 t4_write_reg(adap, ctl_reg, 0); in t4_wr_mbox_meat_timeout() 419 t4_write_reg(adap, ctl_reg, 0); in t4_wr_mbox_meat_timeout()
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