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Searched refs:cru (Results 1 – 25 of 81) sorted by relevance

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/linux/drivers/media/platform/renesas/rzg2l-cru/
H A Drzg2l-core.c41 struct rzg2l_cru_dev *cru = notifier_to_cru(notifier); in rzg2l_cru_group_notify_complete() local
45 ret = rzg2l_cru_ip_subdev_register(cru); in rzg2l_cru_group_notify_complete()
49 ret = v4l2_device_register_subdev_nodes(&cru->v4l2_dev); in rzg2l_cru_group_notify_complete()
51 dev_err(cru->dev, "Failed to register subdev nodes\n"); in rzg2l_cru_group_notify_complete()
55 ret = rzg2l_cru_video_register(cru); in rzg2l_cru_group_notify_complete()
65 source = &cru->csi.subdev->entity; in rzg2l_cru_group_notify_complete()
66 sink = &cru->ip.subdev.entity; in rzg2l_cru_group_notify_complete()
71 dev_err(cru->dev, "Error creating link from %s to %s\n", in rzg2l_cru_group_notify_complete()
75 cru->ip.remote = cru->csi.subdev; in rzg2l_cru_group_notify_complete()
78 source = &cru->ip.subdev.entity; in rzg2l_cru_group_notify_complete()
[all …]
H A DMakefile5 rzg2l-cru-objs = rzg2l-core.o rzg2l-ip.o rzg2l-video.o
6 obj-$(CONFIG_VIDEO_RZG2L_CRU) += rzg2l-cru.o
/linux/arch/arm/boot/dts/rockchip/
H A Drk322x.dtsi7 #include <dt-bindings/clock/rk3228-cru.h>
36 resets = <&cru SRST_CORE0>;
39 clocks = <&cru ARMCLK>;
47 resets = <&cru SRST_CORE1>;
57 resets = <&cru SRST_CORE2>;
67 resets = <&cru SRST_CORE3>;
143 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1_8CH>;
156 clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8CH>;
166 clocks = <&cru SCLK_SPDIF>, <&cru HCLK_SPDIF_8CH>;
180 clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2_2CH>;
[all …]
H A Drk3128.dtsi6 #include <dt-bindings/clock/rk3128-cru.h>
51 clocks = <&cru ARMCLK>;
52 resets = <&cru SRST_CORE0>;
61 resets = <&cru SRST_CORE1>;
69 resets = <&cru SRST_CORE2>;
77 resets = <&cru SRST_CORE3>;
196 clocks = <&cru ACLK_GPU>, <&cru ACLK_GPU>;
199 resets = <&cru SRST_GPU>;
216 clocks = <&cru ACLK_CIF>,
217 <&cru HCLK_CIF>,
[all …]
H A Drk3066a.dtsi9 #include <dt-bindings/clock/rk3066a-cru.h>
41 clocks = <&cru ARMCLK>;
89 clocks = <&cru ACLK_LCDC0>,
90 <&cru DCLK_LCDC0>,
91 <&cru HCLK_LCDC0>;
94 resets = <&cru SRST_LCDC0_AXI>,
95 <&cru SRST_LCDC0_AHB>,
96 <&cru SRST_LCDC0_DCLK>;
115 clocks = <&cru ACLK_LCDC1>,
116 <&cru DCLK_LCDC1>,
[all …]
H A Drk3xxx.dtsi46 clocks = <&cru ACLK_GPU>, <&cru ACLK_GPU>;
48 assigned-clocks = <&cru ACLK_GPU>;
50 resets = <&cru SRST_GPU>;
60 clocks = <&cru ACLK_VDPU>, <&cru HCLK_VDPU>,
61 <&cru ACLK_VEPU>, <&cru HCLK_VEPU>;
82 clocks = <&cru CORE_PERI>;
96 clocks = <&cru CORE_PERI>;
114 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
125 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
173 clocks = <&cru HCLK_OTG0>;
[all …]
H A Drv1108.dtsi6 #include <dt-bindings/clock/rv1108-cru.h>
35 clocks = <&cru ARMCLK>;
102 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
117 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
132 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
146 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
160 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
174 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
186 clocks = <&cru SCLK_SPI>, <&cru PCLK_SPI>;
198 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
[all …]
H A Drk3188.dtsi9 #include <dt-bindings/clock/rk3188-cru.h>
26 clocks = <&cru ARMCLK>;
28 resets = <&cru SRST_CORE0>;
36 resets = <&cru SRST_CORE1>;
44 resets = <&cru SRST_CORE2>;
52 resets = <&cru SRST_CORE3>;
118 clocks = <&cru ACLK_LCDC0>, <&cru DCLK_LCDC0>, <&cru HCLK_LCDC0>;
121 resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>;
135 clocks = <&cru ACLK_LCDC1>, <&cru DCLK_LCDC1>, <&cru HCLK_LCDC1>;
138 resets = <&cru SRST_LCDC1_AXI>, <&cru SRST_LCDC1_AHB>, <&cru SRST_LCDC1_DCLK>;
[all …]
/linux/arch/arm64/boot/dts/rockchip/
H A Drk3328.dtsi6 #include <dt-bindings/clock/rk3328-cru.h>
44 clocks = <&cru ARMCLK>;
63 clocks = <&cru ARMCLK>;
82 clocks = <&cru ARMCLK>;
101 clocks = <&cru ARMCLK>;
246 clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8CH>;
258 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1_8CH>;
270 clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2_2CH>;
282 clocks = <&cru SCLK_SPDIF>, <&cru HCLK_SPDIF_8CH>;
295 clocks = <&cru SCLK_PDM>, <&cru HCLK_PDM>;
[all …]
H A Dpx30.dtsi6 #include <dt-bindings/clock/px30-cru.h>
46 clocks = <&cru ARMCLK>;
58 clocks = <&cru ARMCLK>;
70 clocks = <&cru ARMCLK>;
82 clocks = <&cru ARMCLK>;
269 clocks = <&cru HCLK_HOST>,
270 <&cru HCLK_OTG>,
271 <&cru SCLK_OTG_ADP>;
277 clocks = <&cru HCLK_SDMMC>,
278 <&cru SCLK_SDMMC>;
[all …]
H A Drk3308.dtsi7 #include <dt-bindings/clock/rk3308-cru.h>
51 clocks = <&cru ARMCLK>;
201 assigned-clocks = <&cru USB480M>;
203 clocks = <&cru SCLK_USBPHY_REF>;
245 clocks = <&cru SCLK_I2C0>, <&cru PCLK_I2C0>;
258 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
271 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
284 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
297 clocks = <&cru PCLK_WDT>;
306 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
[all …]
H A Drk3568-fastrhino-r68s.dts30 assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>;
31 assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>;
46 assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
47 assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>;
H A Drk3399-gru-scarlet.dtsi308 clocks = <&cru SCLK_TESTCLKOUT1>;
331 clocks = <&cru SCLK_TESTCLKOUT1>;
366 &cru {
368 <&cru PLL_GPLL>, <&cru PLL_CPLL>,
369 <&cru PLL_NPLL>,
370 <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>,
371 <&cru PCLK_PERIHP>,
372 <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>,
373 <&cru PCLK_PERILP0>, <&cru ACLK_CCI>,
374 <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>,
[all …]
H A Drk3566-radxa-zero-3e.dts18 assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
19 assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru CLK_MAC1_2TOP>;
H A Drk3568-evb1-v10.dts238 assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>;
239 assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>;
254 assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
255 assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>;
321 assigned-clocks = <&cru I2S1_MCLKOUT_TX>;
322 assigned-clock-parents = <&cru CLK_I2S1_8CH_TX>;
325 clocks = <&cru I2S1_MCLKOUT_TX>;
729 assigned-clocks = <&cru DCLK_VOP0>, <&cru PLL_VPLL>, <&cru DCLK_VOP1>;
730 assigned-clock-parents = <&pmucru PLL_HPLL>, <&xin24m>, <&cru PLL_VPLL>;
H A Drk3326-anbernic-rg351m.dtsi104 &cru {
105 assigned-clocks = <&cru PLL_NPLL>,
106 <&cru ACLK_BUS_PRE>, <&cru ACLK_PERI_PRE>,
107 <&cru HCLK_BUS_PRE>, <&cru HCLK_PERI_PRE>,
108 <&cru PCLK_BUS_PRE>, <&cru SCLK_GPU>;
169 clocks = <&cru SCLK_I2S1_OUT>;
H A Drk3566-powkiddy-rk2023.dts15 &cru {
16 assigned-clocks = <&pmucru CLK_RTC_32K>, <&cru PLL_GPLL>,
17 <&pmucru PLL_PPLL>, <&cru PLL_VPLL>;
H A Drk3566-powkiddy-rgb30.dts15 &cru {
16 assigned-clocks = <&pmucru CLK_RTC_32K>, <&cru PLL_GPLL>,
17 <&pmucru PLL_PPLL>, <&cru PLL_VPLL>;
H A Drk3566-lubancat-1.dts426 assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
427 assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru CLK_MAC1_2TOP>;
502 assigned-clocks = <&cru BCLK_EMMC>, <&cru TCLK_EMMC>, <&cru CCLK_EMMC>;
575 assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
576 assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
H A Drk3566-powkiddy-rgb10max3.dts19 &cru {
20 assigned-clocks = <&pmucru CLK_RTC_32K>, <&cru PLL_GPLL>,
21 <&pmucru PLL_PPLL>, <&cru PLL_VPLL>;
H A Drk3566-odroid-m1s.dts178 assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
179 assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru CLK_MAC1_2TOP>;
244 assigned-clocks = <&cru I2S1_MCLKOUT_TX>;
245 assigned-clock-parents = <&cru CLK_I2S1_8CH_TX>;
247 clocks = <&cru I2S1_MCLKOUT_TX>;
649 assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
650 assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
H A Drk3566-quartz64-b.dts176 assigned-clocks = <&cru SCLK_GMAC1_RX_TX>,
177 <&cru SCLK_GMAC1_RGMII_SPEED>,
178 <&cru SCLK_GMAC1>;
179 assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>,
180 <&cru SCLK_GMAC1>,
254 assigned-clocks = <&cru I2S1_MCLKOUT_TX>;
255 assigned-clock-parents = <&cru CLK_I2S1_8CH_TX>;
257 clocks = <&cru I2S1_MCLKOUT_TX>;
731 assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
732 assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
H A Drk3566-orangepi-3b.dtsi156 assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
157 assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru CLK_MAC1_2TOP>;
203 assigned-clocks = <&cru I2S1_MCLKOUT_TX>;
204 assigned-clock-parents = <&cru CLK_I2S1_8CH_TX>;
206 clocks = <&cru I2S1_MCLKOUT_TX>;
669 assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
670 assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
H A Drk3326-odroid-go.dtsi206 &cru {
207 assigned-clocks = <&cru PLL_NPLL>,
208 <&cru ACLK_BUS_PRE>, <&cru ACLK_PERI_PRE>,
209 <&cru HCLK_BUS_PRE>, <&cru HCLK_PERI_PRE>,
210 <&cru PCLK_BUS_PRE>, <&cru SCLK_GPU>;
273 clocks = <&cru SCLK_I2S1_OUT>;
H A Drk3568-easepi-r1.dts165 assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>;
166 assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>;
180 assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
181 assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>;
609 assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
610 assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;

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