| /linux/drivers/gpu/drm/renesas/rcar-du/ |
| H A D | rcar_du_group.c | 108 rcrtc = rcdu->crtcs; in rcar_du_group_setup_didsr()
117 rcrtc = &rcdu->crtcs[rgrp->index * 2]; in rcar_du_group_setup_didsr()
252 struct rcar_du_crtc *rcrtc = &rgrp->dev->crtcs[rgrp->index * 2]; in __rcar_du_group_start_stop()
313 crtc = &rcdu->crtcs[index * 2]; in rcar_du_set_dpad0_vsp1_routing()
357 rcrtc = &rcdu->crtcs[rgrp->index * 2 + i]; in rcar_du_group_set_dpad_levels()
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| H A D | rcar_du_vsp.h | 60 unsigned int crtcs);
72 unsigned int crtcs) in rcar_du_vsp_init() argument
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| H A D | rcar_du_vsp.c | 465 unsigned int crtcs) in rcar_du_vsp_init() argument
469 unsigned int num_crtcs = hweight32(crtcs); in rcar_du_vsp_init()
515 crtcs, &rcar_du_vsp_plane_funcs, in rcar_du_vsp_init()
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| H A D | rcar_du_drv.h | 105 struct rcar_du_crtc crtcs[RCAR_DU_MAX_CRTCS]; member
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| H A D | rcar_du_kms.c | 732 rcdu->crtcs[i].vsp = &rcdu->vsps[j]; in rcar_du_vsps_init()
733 rcdu->crtcs[i].vsp_pipe = cells >= 1 ? args.args[0] : 0; in rcar_du_vsps_init()
985 struct rcar_du_crtc *rcrtc = &rcdu->crtcs[i]; in rcar_du_modeset_init()
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| /linux/drivers/gpu/drm/sun4i/ |
| H A D | sun8i_dw_hdmi.c | 68 u32 crtcs = 0; in sun8i_dw_hdmi_find_possible_crtcs() local
82 crtcs |= drm_of_crtc_port_mask(drm, remote_port); in sun8i_dw_hdmi_find_possible_crtcs()
87 crtcs = drm_of_find_possible_crtcs(drm, node); in sun8i_dw_hdmi_find_possible_crtcs()
93 return crtcs; in sun8i_dw_hdmi_find_possible_crtcs()
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| /linux/drivers/gpu/drm/renesas/rz-du/ |
| H A D | rzg2l_du_vsp.h | 59 unsigned int crtcs);
67 unsigned int crtcs) in rzg2l_du_vsp_init() argument
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| H A D | rzg2l_du_drv.h | 65 struct rzg2l_du_crtc crtcs[RZG2L_DU_MAX_CRTCS]; member
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| H A D | rzg2l_du_kms.c | 377 rcdu->crtcs[i].vsp = &rcdu->vsps[j]; in rzg2l_du_vsps_init()
378 rcdu->crtcs[i].vsp_pipe = cells >= 1 ? args.args[0] : 0; in rzg2l_du_vsps_init()
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| /linux/drivers/gpu/drm/radeon/ |
| H A D | rs690.c | 253 rdev->mode_info.crtcs[0]->lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode1->crtc_hdisplay); in rs690_line_buffer_adjust()
256 rdev->mode_info.crtcs[1]->lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode2->crtc_hdisplay); in rs690_line_buffer_adjust()
599 if (rdev->mode_info.crtcs[0]->base.enabled) in rs690_bandwidth_update()
600 mode0 = &rdev->mode_info.crtcs[0]->base.mode; in rs690_bandwidth_update()
601 if (rdev->mode_info.crtcs[1]->base.enabled) in rs690_bandwidth_update()
602 mode1 = &rdev->mode_info.crtcs[1]->base.mode; in rs690_bandwidth_update()
626 rs690_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[0], &wm0_high, false); in rs690_bandwidth_update()
627 rs690_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[1], &wm1_high, false); in rs690_bandwidth_update()
629 rs690_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[0], &wm0_low, true); in rs690_bandwidth_update()
630 rs690_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[1], &wm1_low, true); in rs690_bandwidth_update()
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| H A D | rv515.c | 1213 if (rdev->mode_info.crtcs[0]->base.enabled) in rv515_bandwidth_avivo_update()
1214 mode0 = &rdev->mode_info.crtcs[0]->base.mode; in rv515_bandwidth_avivo_update()
1215 if (rdev->mode_info.crtcs[1]->base.enabled) in rv515_bandwidth_avivo_update()
1216 mode1 = &rdev->mode_info.crtcs[1]->base.mode; in rv515_bandwidth_avivo_update()
1219 rv515_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[0], &wm0_high, false); in rv515_bandwidth_avivo_update()
1220 rv515_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[1], &wm1_high, false); in rv515_bandwidth_avivo_update()
1222 rv515_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[0], &wm0_low, false); in rv515_bandwidth_avivo_update()
1223 rv515_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[1], &wm1_low, false); in rv515_bandwidth_avivo_update()
1255 if (rdev->mode_info.crtcs[0]->base.enabled) in rv515_bandwidth_update()
1256 mode0 = &rdev->mode_info.crtcs[0]->base.mode; in rv515_bandwidth_update()
[all …]
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| H A D | rs600.c | 121 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id]; in rs600_page_flip()
157 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id]; in rs600_page_flip_pending()
911 if (rdev->mode_info.crtcs[0]->base.enabled) in rs600_bandwidth_update()
912 mode0 = &rdev->mode_info.crtcs[0]->base.mode; in rs600_bandwidth_update()
913 if (rdev->mode_info.crtcs[1]->base.enabled) in rs600_bandwidth_update()
914 mode1 = &rdev->mode_info.crtcs[1]->base.mode; in rs600_bandwidth_update()
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| H A D | radeon_kms.c | 269 crtc = (struct drm_crtc *)minfo->crtcs[i]; in radeon_info_ioctl()
776 if (rdev->mode_info.crtcs[pipe]) { in radeon_get_vblank_counter_kms()
789 &rdev->mode_info.crtcs[pipe]->base.hwmode); in radeon_get_vblank_counter_kms()
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| H A D | radeon_display.c | 284 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id]; in radeon_crtc_handle_vblank()
340 &rdev->mode_info.crtcs[crtc_id]->base.hwmode)) && in radeon_crtc_handle_vblank()
365 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id]; in radeon_crtc_handle_flip()
412 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[work->crtc_id]; in radeon_flip_work_func()
700 rdev->mode_info.crtcs[index] = radeon_crtc; in radeon_crtc_init()
1948 vbl_start -= rdev->mode_info.crtcs[pipe]->lb_vblank_lead_lines; in radeon_get_crtc_scanoutpos()
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| /linux/drivers/gpu/drm/tidss/ |
| H A D | tidss_irq.c | 67 struct drm_crtc *crtc = tidss->crtcs[id]; in tidss_irq_handler()
117 struct tidss_crtc *tcrtc = to_tidss_crtc(tidss->crtcs[i]); in tidss_irq_install()
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| /linux/include/drm/ |
| H A D | drm_lease.h | 25 uint32_t drm_lease_filter_crtcs(struct drm_file *file_priv, uint32_t crtcs);
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| /linux/drivers/gpu/drm/arm/display/komeda/ |
| H A D | komeda_plane.c | 206 crtc = &kms->crtcs[i]; in get_possible_crtcs()
224 kcrtc = &kms->crtcs[i]; in komeda_set_crtc_plane_mask()
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| H A D | komeda_kms.c | 54 komeda_crtc_handle_event(&kms->crtcs[i], &evts); in komeda_kms_irq_handler()
77 struct komeda_crtc *kcrtc = &kms->crtcs[i]; in komeda_kms_atomic_commit_hw_done()
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| H A D | komeda_kms.h | 128 struct komeda_crtc crtcs[KOMEDA_MAX_PIPELINES]; member
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| H A D | komeda_wb_connector.c | 196 err = komeda_wb_connector_add(kms, &kms->crtcs[i]); in komeda_kms_add_wb_connectors()
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| H A D | komeda_crtc.c | 573 crtc = &kms->crtcs[kms->n_crtcs]; in komeda_kms_setup_crtcs()
678 err = komeda_crtc_add(kms, &kms->crtcs[i]); in komeda_kms_add_crtcs()
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| /linux/drivers/gpu/drm/amd/amdgpu/ |
| H A D | dce_v6_0.c | 204 struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id]; in dce_v6_0_page_flip()
1139 if (adev->mode_info.crtcs[i]->base.enabled) in dce_v6_0_bandwidth_update()
1143 mode0 = &adev->mode_info.crtcs[i]->base.mode; in dce_v6_0_bandwidth_update()
1144 mode1 = &adev->mode_info.crtcs[i+1]->base.mode; in dce_v6_0_bandwidth_update()
1145 lb_size = dce_v6_0_line_buffer_adjust(adev, adev->mode_info.crtcs[i], mode0, mode1); in dce_v6_0_bandwidth_update()
1146 dce_v6_0_program_watermarks(adev, adev->mode_info.crtcs[i], lb_size, num_heads); in dce_v6_0_bandwidth_update()
1147 lb_size = dce_v6_0_line_buffer_adjust(adev, adev->mode_info.crtcs[i+1], mode1, mode0); in dce_v6_0_bandwidth_update()
1148 dce_v6_0_program_watermarks(adev, adev->mode_info.crtcs[i+1], lb_size, num_heads); in dce_v6_0_bandwidth_update()
2542 if (adev->mode_info.crtcs[i] && in dce_v6_0_crtc_disable()
2543 adev->mode_info.crtcs[i]->enabled && in dce_v6_0_crtc_disable()
[all …]
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| H A D | dce_v8_0.c | 188 struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id]; in dce_v8_0_page_flip()
1122 if (adev->mode_info.crtcs[i]->base.enabled) in dce_v8_0_bandwidth_update()
1126 mode = &adev->mode_info.crtcs[i]->base.mode; in dce_v8_0_bandwidth_update()
1127 lb_size = dce_v8_0_line_buffer_adjust(adev, adev->mode_info.crtcs[i], mode); in dce_v8_0_bandwidth_update()
1128 dce_v8_0_program_watermarks(adev, adev->mode_info.crtcs[i], in dce_v8_0_bandwidth_update()
2493 if (adev->mode_info.crtcs[i] && in dce_v8_0_crtc_disable()
2494 adev->mode_info.crtcs[i]->enabled && in dce_v8_0_crtc_disable()
2496 amdgpu_crtc->pll_id == adev->mode_info.crtcs[i]->pll_id) { in dce_v8_0_crtc_disable()
2649 adev->mode_info.crtcs[index] = amdgpu_crtc; in dce_v8_0_crtc_init()
3167 amdgpu_crtc = adev->mode_info.crtcs[crtc_id]; in dce_v8_0_pageflip_irq()
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| H A D | dce_v10_0.c | 237 struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id]; in dce_v10_0_page_flip()
1167 if (adev->mode_info.crtcs[i]->base.enabled) in dce_v10_0_bandwidth_update()
1171 mode = &adev->mode_info.crtcs[i]->base.mode; in dce_v10_0_bandwidth_update()
1172 lb_size = dce_v10_0_line_buffer_adjust(adev, adev->mode_info.crtcs[i], mode); in dce_v10_0_bandwidth_update()
1173 dce_v10_0_program_watermarks(adev, adev->mode_info.crtcs[i], in dce_v10_0_bandwidth_update()
2574 if (adev->mode_info.crtcs[i] && in dce_v10_0_crtc_disable()
2575 adev->mode_info.crtcs[i]->enabled && in dce_v10_0_crtc_disable()
2577 amdgpu_crtc->pll_id == adev->mode_info.crtcs[i]->pll_id) { in dce_v10_0_crtc_disable()
2724 adev->mode_info.crtcs[index] = amdgpu_crtc; in dce_v10_0_crtc_init()
3176 amdgpu_crtc = adev->mode_info.crtcs[crtc_id]; in dce_v10_0_pageflip_irq()
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| H A D | atombios_crtc.c | 262 if (adev->mode_info.crtcs[i] && in amdgpu_atombios_crtc_program_ss()
263 adev->mode_info.crtcs[i]->enabled && in amdgpu_atombios_crtc_program_ss()
265 pll_id == adev->mode_info.crtcs[i]->pll_id) { in amdgpu_atombios_crtc_program_ss()
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