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Searched refs:crtc_offsets (Results 1 – 9 of 9) sorted by relevance

/linux/drivers/gpu/drm/radeon/
H A Drv515.c46 static const u32 crtc_offsets[2] = { variable
280 crtc_enabled = RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]) & AVIVO_CRTC_EN; in rv515_mc_stop()
283 tmp = RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]); in rv515_mc_stop()
286 WREG32(AVIVO_D1CRTC_UPDATE_LOCK + crtc_offsets[i], 1); in rv515_mc_stop()
288 WREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i], tmp); in rv515_mc_stop()
289 WREG32(AVIVO_D1CRTC_UPDATE_LOCK + crtc_offsets[i], 0); in rv515_mc_stop()
300 WREG32(AVIVO_D1CRTC_UPDATE_LOCK + crtc_offsets[i], 1); in rv515_mc_stop()
301 tmp = RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]); in rv515_mc_stop()
303 WREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i], tmp); in rv515_mc_stop()
304 WREG32(AVIVO_D1CRTC_UPDATE_LOCK + crtc_offsets[i], 0); in rv515_mc_stop()
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H A Devergreen.c123 static const u32 crtc_offsets[6] = variable
1350 if (RREG32(EVERGREEN_CRTC_STATUS + crtc_offsets[crtc]) & EVERGREEN_CRTC_V_BLANK) in dce4_is_in_vblank()
1360 pos1 = RREG32(EVERGREEN_CRTC_STATUS_POSITION + crtc_offsets[crtc]); in dce4_is_counter_moving()
1361 pos2 = RREG32(EVERGREEN_CRTC_STATUS_POSITION + crtc_offsets[crtc]); in dce4_is_counter_moving()
1384 if (!(RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[crtc]) & EVERGREEN_CRTC_MASTER_EN)) in dce4_wait_for_vblank()
2678 crtc_enabled = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]) & EVERGREEN_CRTC_MASTER_EN; in evergreen_mc_stop()
2682 tmp = RREG32(EVERGREEN_CRTC_BLANK_CONTROL + crtc_offsets[i]); in evergreen_mc_stop()
2685 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 1); in evergreen_mc_stop()
2687 WREG32(EVERGREEN_CRTC_BLANK_CONTROL + crtc_offsets[i], tmp); in evergreen_mc_stop()
2688 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 0); in evergreen_mc_stop()
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H A Drs600.c57 static const u32 crtc_offsets[2] = { variable
64 if (RREG32(AVIVO_D1CRTC_STATUS + crtc_offsets[crtc]) & AVIVO_D1CRTC_V_BLANK) in avivo_is_in_vblank()
74 pos1 = RREG32(AVIVO_D1CRTC_STATUS_POSITION + crtc_offsets[crtc]); in avivo_is_counter_moving()
75 pos2 = RREG32(AVIVO_D1CRTC_STATUS_POSITION + crtc_offsets[crtc]); in avivo_is_counter_moving()
98 if (!(RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[crtc]) & AVIVO_CRTC_EN)) in avivo_wait_for_vblank()
H A Dsi.c141 static const u32 crtc_offsets[] = { variable
5945 WREG32(INT_MASK + crtc_offsets[i], 0); in si_disable_interrupt_state()
5947 WREG32(GRPH_INT_CONTROL + crtc_offsets[i], 0); in si_disable_interrupt_state()
6099 rdev, INT_MASK + crtc_offsets[i], VBLANK_INT_MASK, in si_irq_set()
6105 WREG32(GRPH_INT_CONTROL + crtc_offsets[i], GRPH_PFLIP_INT_MASK); in si_irq_set()
6137 grph_int[i] = RREG32(GRPH_INT_STATUS + crtc_offsets[i]); in si_irq_ack()
6144 WREG32(GRPH_INT_STATUS + crtc_offsets[j], in si_irq_ack()
6150 WREG32(VBLANK_STATUS + crtc_offsets[j], in si_irq_ack()
6153 WREG32(VLINE_STATUS + crtc_offsets[j], in si_irq_ack()
H A Dr600.c103 static const u32 crtc_offsets[2] = { variable
1593 if (RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]) & AVIVO_CRTC_EN) { in r600_is_display_hung()
1594 crtc_status[i] = RREG32(AVIVO_D1CRTC_STATUS_HV_COUNT + crtc_offsets[i]); in r600_is_display_hung()
1602 tmp = RREG32(AVIVO_D1CRTC_STATUS_HV_COUNT + crtc_offsets[i]); in r600_is_display_hung()
/linux/drivers/gpu/drm/amd/amdgpu/
H A Ddce_v10_0.c57 static const u32 crtc_offsets[] = { variable
202 return RREG32(mmCRTC_STATUS_FRAME_COUNT + crtc_offsets[crtc]); in dce_v10_0_vblank_get_counter()
265 *vbl = RREG32(mmCRTC_V_BLANK_START_END + crtc_offsets[crtc]); in dce_v10_0_crtc_get_scanoutpos()
266 *position = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]); in dce_v10_0_crtc_get_scanoutpos()
420 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]); in dce_v10_0_is_display_hung()
422 crtc_status[i] = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]); in dce_v10_0_is_display_hung()
430 tmp = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]); in dce_v10_0_is_display_hung()
491 crtc_enabled = REG_GET_FIELD(RREG32(mmCRTC_CONTROL + crtc_offsets[i]), in dce_v10_0_disable_dce()
494 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1); in dce_v10_0_disable_dce()
495 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]); in dce_v10_0_disable_dce()
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H A Ddce_v11_0.c57 static const u32 crtc_offsets[] = variable
226 return RREG32(mmCRTC_STATUS_FRAME_COUNT + crtc_offsets[crtc]); in dce_v11_0_vblank_get_counter()
289 *vbl = RREG32(mmCRTC_V_BLANK_START_END + crtc_offsets[crtc]); in dce_v11_0_crtc_get_scanoutpos()
290 *position = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]); in dce_v11_0_crtc_get_scanoutpos()
442 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]); in dce_v11_0_is_display_hung()
444 crtc_status[i] = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]); in dce_v11_0_is_display_hung()
452 tmp = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]); in dce_v11_0_is_display_hung()
523 crtc_enabled = REG_GET_FIELD(RREG32(mmCRTC_CONTROL + crtc_offsets[i]), in dce_v11_0_disable_dce()
526 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1); in dce_v11_0_disable_dce()
527 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]); in dce_v11_0_disable_dce()
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H A Ddce_v8_0.c57 static const u32 crtc_offsets[6] = { variable
153 return RREG32(mmCRTC_STATUS_FRAME_COUNT + crtc_offsets[crtc]); in dce_v8_0_vblank_get_counter()
213 *vbl = RREG32(mmCRTC_V_BLANK_START_END + crtc_offsets[crtc]); in dce_v8_0_crtc_get_scanoutpos()
214 *position = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]); in dce_v8_0_crtc_get_scanoutpos()
372 if (RREG32(mmCRTC_CONTROL + crtc_offsets[i]) & CRTC_CONTROL__CRTC_MASTER_EN_MASK) { in dce_v8_0_is_display_hung()
373 crtc_status[i] = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]); in dce_v8_0_is_display_hung()
381 tmp = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]); in dce_v8_0_is_display_hung()
449 crtc_enabled = REG_GET_FIELD(RREG32(mmCRTC_CONTROL + crtc_offsets[i]), in dce_v8_0_disable_dce()
452 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1); in dce_v8_0_disable_dce()
453 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]); in dce_v8_0_disable_dce()
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H A Ddce_v6_0.c60 static const u32 crtc_offsets[6] = variable
159 return RREG32(mmCRTC_STATUS_FRAME_COUNT + crtc_offsets[crtc]); in dce_v6_0_vblank_get_counter()
221 *vbl = RREG32(mmCRTC_V_BLANK_START_END + crtc_offsets[crtc]); in dce_v6_0_crtc_get_scanoutpos()
222 *position = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]); in dce_v6_0_crtc_get_scanoutpos()
407 crtc_enabled = RREG32(mmCRTC_CONTROL + crtc_offsets[i]) & in dce_v6_0_disable_dce()
410 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1); in dce_v6_0_disable_dce()
411 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]); in dce_v6_0_disable_dce()
413 WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp); in dce_v6_0_disable_dce()
414 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0); in dce_v6_0_disable_dce()
2651 amdgpu_crtc->crtc_offset = crtc_offsets[amdgpu_crtc->crtc_id]; in dce_v6_0_crtc_init()
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