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Searched refs:cqc (Results 1 – 16 of 16) sorted by relevance

/linux/drivers/net/ethernet/mellanox/mlx5/core/
H A Dwc.c48 static int mlx5_wc_create_cqwq(struct mlx5_core_dev *mdev, void *cqc, in mlx5_wc_create_cqwq() argument
56 err = mlx5_cqwq_create(mdev, &param, cqc, &cq->wq, &cq->wq_ctrl); in mlx5_wc_create_cqwq()
81 void *in, *cqc; in create_wc_cq() local
93 cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context); in create_wc_cq()
95 memcpy(cqc, cqc_data, MLX5_ST_SZ_BYTES(cqc)); in create_wc_cq()
100 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE); in create_wc_cq()
101 MLX5_SET(cqc, cqc, c_eqn_or_apu_element, eqn); in create_wc_cq()
102 MLX5_SET(cqc, cqc, uar_page, mdev->priv.bfreg.up->index); in create_wc_cq()
103 MLX5_SET(cqc, cqc, log_page_size, cq->wq_ctrl.buf.page_shift - in create_wc_cq()
105 MLX5_SET64(cqc, cqc, dbr_addr, cq->wq_ctrl.db.dma); in create_wc_cq()
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H A Dcq.c111 int eqn = MLX5_GET(cqc, MLX5_ADDR_OF(create_cq_in, in, cq_context), in mlx5_create_cq()
243 void *cqc; in mlx5_core_modify_cq_moderation() local
246 cqc = MLX5_ADDR_OF(modify_cq_in, in, cq_context); in mlx5_core_modify_cq_moderation()
247 MLX5_SET(cqc, cqc, cq_period, cq_period); in mlx5_core_modify_cq_moderation()
248 MLX5_SET(cqc, cqc, cq_max_count, cq_max_count); in mlx5_core_modify_cq_moderation()
H A Dwq.c160 void *cqc, struct mlx5_cqwq *wq, in mlx5_cqwq_create() argument
164 u8 log_wq_stride = MLX5_GET(cqc, cqc, cqe_sz) == CQE_STRIDE_64 ? 6 : 7; in mlx5_cqwq_create()
165 u8 log_wq_sz = MLX5_GET(cqc, cqc, log_cq_size); in mlx5_cqwq_create()
H A Ddebugfs.c448 param = 1 << MLX5_GET(cqc, ctx, log_cq_size); in cq_read_field()
451 param = MLX5_GET(cqc, ctx, log_page_size); in cq_read_field()
/linux/drivers/infiniband/hw/mlx5/
H A Dcq.c729 void *cqc; in create_cq_user() local
761 cq->buf.umem, cqc, log_page_size, MLX5_ADAPTER_PAGE_SHIFT, in create_cq_user()
790 cqc = MLX5_ADDR_OF(create_cq_in, *cqb, cq_context); in create_cq_user()
791 MLX5_SET(cqc, cqc, log_page_size, in create_cq_user()
793 MLX5_SET(cqc, cqc, page_offset, page_offset_quantized); in create_cq_user()
831 MLX5_SET(cqc, cqc, cqe_comp_en, 1); in create_cq_user()
832 MLX5_SET(cqc, cqc, mini_cqe_res_format, mini_cqe_format); in create_cq_user()
892 void *cqc; in create_cq_kernel() local
921 cqc = MLX5_ADDR_OF(create_cq_in, *cqb, cq_context); in create_cq_kernel()
922 MLX5_SET(cqc, cqc, log_page_size, in create_cq_kernel()
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H A Ddevx.c743 void *cqc; in devx_set_umem_valid() local
746 cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context); in devx_set_umem_valid()
747 MLX5_SET(cqc, cqc, dbr_umem_valid, 1); in devx_set_umem_valid()
1518 !MLX5_GET(cqc, MLX5_ADDR_OF(create_cq_in, in, cq_context), apu_cq)) in is_apu_cq()
/linux/drivers/net/ethernet/mellanox/mlx5/core/en/
H A Dparams.c813 void *cqc = param->cqc; in mlx5e_build_common_cq_param() local
815 MLX5_SET(cqc, cqc, uar_page, mdev->priv.bfreg.up->index); in mlx5e_build_common_cq_param()
817 MLX5_SET(cqc, cqc, cqe_sz, CQE_STRIDE_128_PAD); in mlx5e_build_common_cq_param()
843 void *cqc = param->cqc; in mlx5e_build_rx_cq_param() local
859 MLX5_SET(cqc, cqc, log_cq_size, log_cq_size); in mlx5e_build_rx_cq_param()
861 MLX5_SET(cqc, cqc, mini_cqe_res_format, hw_stridx ? in mlx5e_build_rx_cq_param()
863 MLX5_SET(cqc, cqc, cqe_compression_layout, in mlx5e_build_rx_cq_param()
867 MLX5_SET(cqc, cqc, cqe_comp_en, 1); in mlx5e_build_rx_cq_param()
979 void *cqc = param->cqc; in mlx5e_build_tx_cq_param() local
981 MLX5_SET(cqc, cqc, log_cq_size, params->log_sq_size); in mlx5e_build_tx_cq_param()
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/linux/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/
H A Dsend.c916 void *in, *cqc; in hws_send_ring_create_cq() local
930 cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context); in hws_send_ring_create_cq()
931 memcpy(cqc, cqc_data, MLX5_ST_SZ_BYTES(cqc)); in hws_send_ring_create_cq()
935 MLX5_SET(cqc, cqc, c_eqn_or_apu_element, eqn); in hws_send_ring_create_cq()
936 MLX5_SET(cqc, cqc, uar_page, mdev->priv.bfreg.up->index); in hws_send_ring_create_cq()
937 MLX5_SET(cqc, cqc, log_page_size, cq->wq_ctrl.buf.page_shift - MLX5_ADAPTER_PAGE_SHIFT); in hws_send_ring_create_cq()
938 MLX5_SET64(cqc, cqc, dbr_addr, cq->wq_ctrl.db.dma); in hws_send_ring_create_cq()
955 cqc_data = kvzalloc(MLX5_ST_SZ_BYTES(cqc), GFP_KERNEL); in hws_send_ring_open_cq()
959 MLX5_SET(cqc, cqc_data, uar_page, mdev->priv.bfreg.up->index); in hws_send_ring_open_cq()
960 MLX5_SET(cqc, cqc_data, log_cq_size, ilog2(queue->num_entries)); in hws_send_ring_open_cq()
/linux/drivers/net/ethernet/mellanox/mlx5/core/fpga/
H A Dconn.c415 u32 temp_cqc[MLX5_ST_SZ_DW(cqc)] = {0}; in mlx5_fpga_conn_create_cq()
420 void *cqc, *in; in mlx5_fpga_conn_create_cq() local
432 MLX5_SET(cqc, temp_cqc, log_cq_size, ilog2(cq_size)); in mlx5_fpga_conn_create_cq()
461 cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context); in mlx5_fpga_conn_create_cq()
462 MLX5_SET(cqc, cqc, log_cq_size, ilog2(cq_size)); in mlx5_fpga_conn_create_cq()
463 MLX5_SET(cqc, cqc, c_eqn_or_apu_element, eqn); in mlx5_fpga_conn_create_cq()
464 MLX5_SET(cqc, cqc, uar_page, fdev->conn_res.uar->index); in mlx5_fpga_conn_create_cq()
465 MLX5_SET(cqc, cqc, log_page_size, conn->cq.wq_ctrl.buf.page_shift - in mlx5_fpga_conn_create_cq()
467 MLX5_SET64(cqc, cqc, dbr_addr, conn->cq.wq_ctrl.db.dma); in mlx5_fpga_conn_create_cq()
/linux/drivers/net/ethernet/mellanox/mlx5/core/steering/sws/
H A Ddr_send.c1056 u32 temp_cqc[MLX5_ST_SZ_DW(cqc)] = {}; in dr_create_cq()
1062 void *cqc, *in; in dr_create_cq() local
1071 MLX5_SET(cqc, temp_cqc, log_cq_size, ilog2(ncqe)); in dr_create_cq()
1105 cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context); in dr_create_cq()
1106 MLX5_SET(cqc, cqc, log_cq_size, ilog2(ncqe)); in dr_create_cq()
1107 MLX5_SET(cqc, cqc, c_eqn_or_apu_element, eqn); in dr_create_cq()
1108 MLX5_SET(cqc, cqc, uar_page, uar->index); in dr_create_cq()
1109 MLX5_SET(cqc, cqc, log_page_size, cq->wq_ctrl.buf.page_shift - in dr_create_cq()
1111 MLX5_SET64(cqc, cqc, dbr_addr, cq->wq_ctrl.db.dma); in dr_create_cq()
/linux/include/linux/mlx5/
H A Dcq.h132 #define MLX5_MAX_CQ_PERIOD (BIT(__mlx5_bit_sz(cqc, cq_period)) - 1)
133 #define MLX5_MAX_CQ_COUNT (BIT(__mlx5_bit_sz(cqc, cq_max_count)) - 1)
/linux/drivers/vfio/pci/mlx5/
H A Dcmd.c1161 void *cqc, *in; in mlx5vf_create_cq() local
1194 cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context); in mlx5vf_create_cq()
1195 MLX5_SET(cqc, cqc, log_cq_size, ilog2(ncqe)); in mlx5vf_create_cq()
1196 MLX5_SET(cqc, cqc, c_eqn_or_apu_element, eqn); in mlx5vf_create_cq()
1197 MLX5_SET(cqc, cqc, uar_page, tracker->uar->index); in mlx5vf_create_cq()
1198 MLX5_SET(cqc, cqc, log_page_size, cq->buf.frag_buf.page_shift - in mlx5vf_create_cq()
1200 MLX5_SET64(cqc, cqc, dbr_addr, cq->db.dma); in mlx5vf_create_cq()
/linux/drivers/crypto/hisilicon/
H A Dqm.c61 #define QM_CQ_TAIL_IDX(cqc) ((le16_to_cpu((cqc).w11) >> 6) & 0x1) argument
689 tmp_xqc = qm->xqc_buf.cqc; in qm_set_and_get_xqc()
2121 struct qm_cqc cqc = {0}; in qm_cq_ctx_cfg() local
2124 cqc.dw3 = cpu_to_le32(QM_MK_CQC_DW3_V1(0, 0, 0, QM_QC_CQE_SIZE)); in qm_cq_ctx_cfg()
2125 cqc.w8 = cpu_to_le16(qp->cq_depth - 1); in qm_cq_ctx_cfg()
2127 cqc.dw3 = cpu_to_le32(QM_MK_CQC_DW3_V2(QM_QC_CQE_SIZE, qp->cq_depth)); in qm_cq_ctx_cfg()
2128 cqc.w8 = 0; /* rand_qc */ in qm_cq_ctx_cfg()
2135 cqc.dw6 = cpu_to_le32(1 << QM_CQ_PHASE_SHIFT | 1 << QM_CQ_FLAG_SHIFT); in qm_cq_ctx_cfg()
2136 cqc.base_l = cpu_to_le32(lower_32_bits(qp->cqe_dma)); in qm_cq_ctx_cfg()
2137 cqc.base_h = cpu_to_le32(upper_32_bits(qp->cqe_dma)); in qm_cq_ctx_cfg()
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/linux/include/linux/
H A Dhisi_acc_qm.h352 struct qm_cqc *cqc; member
387 struct qm_cqc *cqc; member
/linux/drivers/vdpa/mlx5/net/
H A Dmlx5_vnet.c564 void *cqc; in cq_create() local
597 cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context); in cq_create()
598 MLX5_SET(cqc, cqc, log_page_size, vcq->buf.frag_buf.page_shift - MLX5_ADAPTER_PAGE_SHIFT); in cq_create()
607 cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context); in cq_create()
608 MLX5_SET(cqc, cqc, log_cq_size, ilog2(num_ent)); in cq_create()
609 MLX5_SET(cqc, cqc, uar_page, ndev->mvdev.res.uar->index); in cq_create()
610 MLX5_SET(cqc, cqc, c_eqn_or_apu_element, eqn); in cq_create()
611 MLX5_SET64(cqc, cqc, dbr_addr, vcq->db.dma); in cq_create()
/linux/drivers/net/ethernet/mellanox/mlx4/
H A Dresource_tracker.c3077 static int cq_get_mtt_addr(struct mlx4_cq_context *cqc) in cq_get_mtt_addr() argument
3079 return be32_to_cpu(cqc->mtt_base_addr_l) & 0xfffffff8; in cq_get_mtt_addr()
3082 static int cq_get_mtt_size(struct mlx4_cq_context *cqc) in cq_get_mtt_size() argument
3084 int log_cq_size = (be32_to_cpu(cqc->logsize_usrpage) >> 24) & 0x1f; in cq_get_mtt_size()
3085 int page_shift = (cqc->log_page_size & 0x3f) + 12; in cq_get_mtt_size()
3442 struct mlx4_cq_context *cqc = inbox->buf; in mlx4_SW2HW_CQ_wrapper() local
3443 int mtt_base = cq_get_mtt_addr(cqc) / dev->caps.mtt_entry_sz; in mlx4_SW2HW_CQ_wrapper()
3453 err = check_mtt_range(dev, slave, mtt_base, cq_get_mtt_size(cqc), mtt); in mlx4_SW2HW_CQ_wrapper()
3531 struct mlx4_cq_context *cqc = inbox->buf; in handle_resize() local
3532 int mtt_base = cq_get_mtt_addr(cqc) / dev->caps.mtt_entry_sz; in handle_resize()
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