| /linux/drivers/clk/pxa/ |
| H A D | clk-pxa.c | 221 rate = freqs[i].cpll; in pxa2xx_determine_rate()
239 rate = freqs[closest_below].cpll; in pxa2xx_determine_rate()
241 rate = freqs[closest_above].cpll; in pxa2xx_determine_rate()
|
| H A D | clk-pxa.h | 137 unsigned long cpll; member
|
| H A D | clk-pxa25x.c | 244 if (pxa25x_freqs[i].cpll == rate) in clk_pxa25x_cpll_set_rate()
|
| H A D | clk-pxa27x.c | 235 if (pxa27x_freqs[i].cpll == rate) in clk_pxa27x_cpll_set_rate()
|
| /linux/drivers/clk/rockchip/ |
| H A D | clk-rk3128.c | 18 apll, dpll, cpll, gpll, enumerator
163 [cpll] = PLL(pll_rk3036, PLL_CPLL, "cpll", mux_pll_p, 0, RK2928_PLL_CON(8),
|
| H A D | clk-rk3228.c | 19 apll, dpll, cpll, gpll, enumerator
173 [cpll] = PLL(pll_rk3036, PLL_CPLL, "cpll", mux_pll_p, 0, RK2928_PLL_CON(6),
|
| H A D | clk-rk3328.c | 21 apll, dpll, cpll, gpll, npll, enumerator
221 [cpll] = PLL(pll_rk3328, PLL_CPLL, "cpll", mux_pll_p,
|
| H A D | clk-rk3368.c | 17 apllb, aplll, dpll, cpll, gpll, npll, enumerator
136 [cpll] = PLL(pll_rk3066, PLL_CPLL, "cpll", mux_pll_p, 0, RK3368_PLL_CON(12),
|
| H A D | clk-rk3288.c | 24 apll, dpll, cpll, gpll, npll, enumerator
230 [cpll] = PLL(pll_rk3066, PLL_CPLL, "cpll", mux_pll_p, 0, RK3288_PLL_CON(8),
|
| H A D | clk-px30.c | 18 apll, dpll, cpll, npll, apll_b_h, apll_b_l, enumerator
191 [cpll] = PLL(pll_rk3328, PLL_CPLL, "cpll", mux_pll_p,
|
| H A D | clk-rv1126.c | 28 apll, dpll, cpll, hpll, enumerator
203 [cpll] = PLL(pll_rk3328, PLL_CPLL, "cpll", mux_pll_p,
|
| H A D | clk-rk3528.c | 24 apll, cpll, gpll, ppll, dpll, enumerator
186 [cpll] = PLL(pll_rk3328, PLL_CPLL, "cpll", mux_pll_p,
|
| H A D | clk-rv1126b.c | 24 gpll, cpll, aupll, dpll enumerator
167 [cpll] = PLL(pll_rk3328, PLL_CPLL, "cpll", mux_pll_p,
|
| H A D | clk-rk3399.c | 19 lpll, bpll, dpll, cpll, gpll, npll, vpll, enumerator
225 [cpll] = PLL(pll_rk3399, PLL_CPLL, "cpll", mux_pll_p, 0, RK3399_PLL_CON(24),
|
| H A D | clk-rk3568.c | 23 apll, dpll, gpll, cpll, npll, vpll, enumerator
336 [cpll] = PLL(pll_rk3328, PLL_CPLL, "cpll", mux_pll_p,
|
| H A D | clk-rk3576.c | 22 bpll, lpll, vpll, aupll, cpll, gpll, ppll, enumerator
377 [cpll] = PLL(pll_rk3588, PLL_CPLL, "cpll", mux_pll_p,
|
| H A D | clk-rk3588.c | 19 b0pll, b1pll, lpll, v0pll, aupll, cpll, gpll, npll, ppll, enumerator
664 [cpll] = PLL(pll_rk3588, PLL_CPLL, "cpll", mux_pll_p,
|
| /linux/arch/arm64/boot/dts/rockchip/ |
| H A D | rk3328.dtsi | 860 * We need set cpll child clk div first,
861 * and then set the cpll frequency.
|