/linux/drivers/gpu/drm/amd/amdgpu/ |
H A D | gfx_v6_0.c | 3196 u32 cp_int_cntl; in gfx_v6_0_set_gfx_eop_interrupt_state() local 3200 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); in gfx_v6_0_set_gfx_eop_interrupt_state() 3201 cp_int_cntl &= ~CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK; in gfx_v6_0_set_gfx_eop_interrupt_state() 3202 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); in gfx_v6_0_set_gfx_eop_interrupt_state() 3205 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); in gfx_v6_0_set_gfx_eop_interrupt_state() 3206 cp_int_cntl |= CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK; in gfx_v6_0_set_gfx_eop_interrupt_state() 3207 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); in gfx_v6_0_set_gfx_eop_interrupt_state() 3218 u32 cp_int_cntl; in gfx_v6_0_set_compute_eop_interrupt_state() local 3222 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING1); in gfx_v6_0_set_compute_eop_interrupt_state() 3223 cp_int_cntl &= ~CP_INT_CNTL_RING1__TIME_STAMP_INT_ENABLE_MASK; in gfx_v6_0_set_compute_eop_interrupt_state() [all …]
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H A D | gfx_v12_0.c | 4670 uint32_t cp_int_cntl, cp_int_cntl_reg; in gfx_v12_0_set_gfx_eop_interrupt_state() local 4688 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); in gfx_v12_0_set_gfx_eop_interrupt_state() 4689 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, in gfx_v12_0_set_gfx_eop_interrupt_state() 4691 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, in gfx_v12_0_set_gfx_eop_interrupt_state() 4693 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); in gfx_v12_0_set_gfx_eop_interrupt_state() 4696 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); in gfx_v12_0_set_gfx_eop_interrupt_state() 4697 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, in gfx_v12_0_set_gfx_eop_interrupt_state() 4699 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, in gfx_v12_0_set_gfx_eop_interrupt_state() 4701 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); in gfx_v12_0_set_gfx_eop_interrupt_state() 4849 u32 cp_int_cntl_reg, cp_int_cntl; in gfx_v12_0_set_priv_reg_fault_state() local [all …]
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H A D | gfx_v11_0.c | 6170 uint32_t cp_int_cntl, cp_int_cntl_reg; in gfx_v11_0_set_gfx_eop_interrupt_state() local 6191 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); in gfx_v11_0_set_gfx_eop_interrupt_state() 6192 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, in gfx_v11_0_set_gfx_eop_interrupt_state() 6194 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, in gfx_v11_0_set_gfx_eop_interrupt_state() 6196 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); in gfx_v11_0_set_gfx_eop_interrupt_state() 6199 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); in gfx_v11_0_set_gfx_eop_interrupt_state() 6200 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, in gfx_v11_0_set_gfx_eop_interrupt_state() 6202 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, in gfx_v11_0_set_gfx_eop_interrupt_state() 6204 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); in gfx_v11_0_set_gfx_eop_interrupt_state() 6358 u32 cp_int_cntl_reg, cp_int_cntl; in gfx_v11_0_set_priv_reg_fault_state() local [all …]
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H A D | gfx_v7_0.c | 4627 u32 cp_int_cntl; in gfx_v7_0_set_gfx_eop_interrupt_state() local 4631 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); in gfx_v7_0_set_gfx_eop_interrupt_state() 4632 cp_int_cntl &= ~CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK; in gfx_v7_0_set_gfx_eop_interrupt_state() 4633 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); in gfx_v7_0_set_gfx_eop_interrupt_state() 4636 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); in gfx_v7_0_set_gfx_eop_interrupt_state() 4637 cp_int_cntl |= CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK; in gfx_v7_0_set_gfx_eop_interrupt_state() 4638 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); in gfx_v7_0_set_gfx_eop_interrupt_state() 4701 u32 cp_int_cntl; in gfx_v7_0_set_priv_reg_fault_state() local 4705 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); in gfx_v7_0_set_priv_reg_fault_state() 4706 cp_int_cntl &= ~CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK; in gfx_v7_0_set_priv_reg_fault_state() [all …]
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H A D | gfx_v10_0.c | 9007 uint32_t cp_int_cntl, cp_int_cntl_reg; in gfx_v10_0_set_gfx_eop_interrupt_state() local 9028 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); in gfx_v10_0_set_gfx_eop_interrupt_state() 9029 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, in gfx_v10_0_set_gfx_eop_interrupt_state() 9031 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); in gfx_v10_0_set_gfx_eop_interrupt_state() 9034 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); in gfx_v10_0_set_gfx_eop_interrupt_state() 9035 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, in gfx_v10_0_set_gfx_eop_interrupt_state() 9037 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); in gfx_v10_0_set_gfx_eop_interrupt_state() 9184 u32 cp_int_cntl_reg, cp_int_cntl; in gfx_v10_0_set_priv_reg_fault_state() local 9195 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); in gfx_v10_0_set_priv_reg_fault_state() 9196 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, in gfx_v10_0_set_priv_reg_fault_state() [all …]
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H A D | gfx_v9_0.c | 6078 u32 cp_int_cntl_reg, cp_int_cntl; in gfx_v9_0_set_priv_reg_fault_state() local 6093 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); in gfx_v9_0_set_priv_reg_fault_state() 6094 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_ME1_PIPE0_INT_CNTL, in gfx_v9_0_set_priv_reg_fault_state() 6097 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); in gfx_v9_0_set_priv_reg_fault_state() 6114 u32 cp_int_cntl_reg, cp_int_cntl; in gfx_v9_0_set_bad_op_fault_state() local 6129 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); in gfx_v9_0_set_bad_op_fault_state() 6130 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_ME1_PIPE0_INT_CNTL, in gfx_v9_0_set_bad_op_fault_state() 6133 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); in gfx_v9_0_set_bad_op_fault_state()
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/linux/drivers/gpu/drm/radeon/ |
H A D | ni.h | 32 int ring, u32 cp_int_cntl);
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H A D | evergreen.c | 4493 u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE; in evergreen_irq_set() local 4524 cp_int_cntl |= TIME_STAMP_INT_ENABLE; in evergreen_irq_set() 4537 cp_int_cntl |= RB_INT_ENABLE; in evergreen_irq_set() 4538 cp_int_cntl |= TIME_STAMP_INT_ENABLE; in evergreen_irq_set() 4561 cayman_cp_int_cntl_setup(rdev, 0, cp_int_cntl); in evergreen_irq_set() 4565 WREG32(CP_INT_CNTL, cp_int_cntl); in evergreen_irq_set()
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H A D | ni.c | 1367 int ring, u32 cp_int_cntl) in cayman_cp_int_cntl_setup() argument 1370 WREG32(CP_INT_CNTL, cp_int_cntl); in cayman_cp_int_cntl_setup()
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H A D | r600.c | 3763 u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE; in r600_irq_set() local 3821 cp_int_cntl |= RB_INT_ENABLE; in r600_irq_set() 3822 cp_int_cntl |= TIME_STAMP_INT_ENABLE; in r600_irq_set() 3873 WREG32(CP_INT_CNTL, cp_int_cntl); in r600_irq_set()
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H A D | si.c | 6033 u32 cp_int_cntl; in si_irq_set() local 6051 cp_int_cntl = RREG32(CP_INT_CNTL_RING0) & in si_irq_set() 6063 cp_int_cntl |= TIME_STAMP_INT_ENABLE; in si_irq_set() 6083 WREG32(CP_INT_CNTL_RING0, cp_int_cntl); in si_irq_set()
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H A D | cik.c | 7017 u32 cp_int_cntl; in cik_irq_set() local 7037 cp_int_cntl = RREG32(CP_INT_CNTL_RING0) & in cik_irq_set() 7039 cp_int_cntl |= PRIV_INSTR_INT_ENABLE | PRIV_REG_INT_ENABLE; in cik_irq_set() 7063 cp_int_cntl |= TIME_STAMP_INT_ENABLE; in cik_irq_set() 7217 WREG32(CP_INT_CNTL_RING0, cp_int_cntl); in cik_irq_set()
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