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Searched refs:cp_int_cntl (Results 1 – 5 of 5) sorted by relevance

/linux/drivers/gpu/drm/radeon/
H A Dni.h32 int ring, u32 cp_int_cntl);
H A Dni.c1367 int ring, u32 cp_int_cntl) in cayman_cp_int_cntl_setup() argument
1370 WREG32(CP_INT_CNTL, cp_int_cntl); in cayman_cp_int_cntl_setup()
H A Dr600.c3763 u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE; in r600_irq_set() local
3821 cp_int_cntl |= RB_INT_ENABLE; in r600_irq_set()
3822 cp_int_cntl |= TIME_STAMP_INT_ENABLE; in r600_irq_set()
3873 WREG32(CP_INT_CNTL, cp_int_cntl); in r600_irq_set()
/linux/drivers/gpu/drm/amd/amdgpu/
H A Dgfx_v10_0.c9061 uint32_t cp_int_cntl, cp_int_cntl_reg; in gfx_v10_0_set_gfx_eop_interrupt_state() local
9082 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); in gfx_v10_0_set_gfx_eop_interrupt_state()
9083 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, in gfx_v10_0_set_gfx_eop_interrupt_state()
9085 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); in gfx_v10_0_set_gfx_eop_interrupt_state()
9088 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); in gfx_v10_0_set_gfx_eop_interrupt_state()
9089 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, in gfx_v10_0_set_gfx_eop_interrupt_state()
9091 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); in gfx_v10_0_set_gfx_eop_interrupt_state()
9238 u32 cp_int_cntl_reg, cp_int_cntl; in gfx_v10_0_set_priv_reg_fault_state() local
9249 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); in gfx_v10_0_set_priv_reg_fault_state()
9250 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, in gfx_v10_0_set_priv_reg_fault_state()
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H A Dgfx_v9_0.c6102 u32 cp_int_cntl_reg, cp_int_cntl; in gfx_v9_0_set_priv_reg_fault_state() local
6117 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); in gfx_v9_0_set_priv_reg_fault_state()
6118 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_ME1_PIPE0_INT_CNTL, in gfx_v9_0_set_priv_reg_fault_state()
6121 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); in gfx_v9_0_set_priv_reg_fault_state()
6138 u32 cp_int_cntl_reg, cp_int_cntl; in gfx_v9_0_set_bad_op_fault_state() local
6153 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); in gfx_v9_0_set_bad_op_fault_state()
6154 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_ME1_PIPE0_INT_CNTL, in gfx_v9_0_set_bad_op_fault_state()
6157 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); in gfx_v9_0_set_bad_op_fault_state()