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Searched refs:cp_hqd_pq_base_lo (Results 1 – 21 of 21) sorted by relevance

/linux/drivers/gpu/drm/amd/amdkfd/
H A Dkfd_mqd_manager_cik.c192 m->cp_hqd_pq_base_lo = lower_32_bits((uint64_t)q->queue_address >> 8); in __update_mqd()
352 m->cp_hqd_pq_base_lo = lower_32_bits((uint64_t)q->queue_address >> 8); in update_mqd_hiq()
H A Dkfd_mqd_manager_v12.c194 m->cp_hqd_pq_base_lo = lower_32_bits((uint64_t)q->queue_address >> 8); in update_mqd()
H A Dkfd_mqd_manager_vi.c184 m->cp_hqd_pq_base_lo = lower_32_bits((uint64_t)q->queue_address >> 8); in __update_mqd()
H A Dkfd_mqd_manager_v10.c178 m->cp_hqd_pq_base_lo = lower_32_bits((uint64_t)q->queue_address >> 8); in update_mqd()
H A Dkfd_mqd_manager_v11.c231 m->cp_hqd_pq_base_lo = lower_32_bits((uint64_t)q->queue_address >> 8); in update_mqd()
H A Dkfd_mqd_manager_v9.c255 m->cp_hqd_pq_base_lo = lower_32_bits((uint64_t)q->queue_address >> 8); in update_mqd()
/linux/drivers/gpu/drm/amd/include/
H A Dcik_structs.h87 uint32_t cp_hqd_pq_base_lo; member
H A Dvi_structs.h296 uint32_t cp_hqd_pq_base_lo; member
H A Dv9_structs.h306 uint32_t cp_hqd_pq_base_lo; member
H A Dv11_structs.h811 uint32_t cp_hqd_pq_base_lo; // offset: 136 (0x88) member
H A Dv12_structs.h811 uint32_t cp_hqd_pq_base_lo; // offset: 136 (0x88) member
H A Dv10_structs.h812 uint32_t cp_hqd_pq_base_lo; member
/linux/drivers/gpu/drm/amd/amdgpu/
H A Dmes_v11_0.c1125 mqd->cp_hqd_pq_base_lo = lower_32_bits(hqd_gpu_addr); in mes_v11_0_mqd_init()
1215 WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE, mqd->cp_hqd_pq_base_lo); in mes_v11_0_queue_init_register()
H A Dmes_v12_0.c1206 mqd->cp_hqd_pq_base_lo = lower_32_bits(hqd_gpu_addr); in mes_v12_0_mqd_init()
1303 WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE, mqd->cp_hqd_pq_base_lo); in mes_v12_0_queue_init_register()
H A Dgfx_v9_4_3.c1888 mqd->cp_hqd_pq_base_lo = hqd_gpu_addr; in gfx_v9_4_3_xcc_mqd_init()
1999 mqd->cp_hqd_pq_base_lo); in gfx_v9_4_3_xcc_kiq_init_register()
H A Dgfx_v12_0.c3092 mqd->cp_hqd_pq_base_lo = hqd_gpu_addr; in gfx_v12_0_compute_mqd_init()
3216 mqd->cp_hqd_pq_base_lo); in gfx_v12_0_kiq_init_register()
H A Dgfx_v11_0.c4169 mqd->cp_hqd_pq_base_lo = hqd_gpu_addr; in gfx_v11_0_compute_mqd_init()
4294 mqd->cp_hqd_pq_base_lo); in gfx_v11_0_kiq_init_register()
H A Dgfx_v9_0.c3591 mqd->cp_hqd_pq_base_lo = hqd_gpu_addr; in gfx_v9_0_mqd_init()
3701 mqd->cp_hqd_pq_base_lo); in gfx_v9_0_kiq_init_register()
H A Dgfx_v7_0.c2855 mqd->cp_hqd_pq_base_lo = hqd_gpu_addr; in gfx_v7_0_mqd_init()
H A Dgfx_v10_0.c6873 mqd->cp_hqd_pq_base_lo = hqd_gpu_addr; in gfx_v10_0_compute_mqd_init()
6983 mqd->cp_hqd_pq_base_lo); in gfx_v10_0_kiq_init_register()
H A Dgfx_v8_0.c4469 mqd->cp_hqd_pq_base_lo = hqd_gpu_addr; in gfx_v8_0_mqd_init()