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/linux/Documentation/admin-guide/
H A Dlockup-watchdogs.rst67 By default, the watchdog runs on all online cores. However, on a
69 on the housekeeping cores, not the cores specified in the "nohz_full"
71 the "nohz_full" cores, we would have to run timer ticks to activate
73 from protecting the user code on those cores from the kernel.
74 Of course, disabling it by default on the nohz_full cores means that
75 when those cores do enter the kernel, by default we will not be
77 to continue to run on the housekeeping (non-tickless) cores means
78 that we will continue to detect lockups properly on those cores.
80 In either case, the set of cores excluded from running the watchdog
82 nohz_full cores, this may be useful for debugging a case where the
[all …]
/linux/Documentation/networking/device_drivers/can/freescale/
H A Dflexcan.rst13 For most flexcan IP cores the driver supports 2 RX modes:
18 The older flexcan cores (integrated into the i.MX25, i.MX28, i.MX35
28 cores come up in a mode where RTR reception is possible.
39 On some IP cores the controller cannot receive RTR frames in the
45 Waive ability to receive RTR frames. (not supported on all IP cores)
48 some IP cores RTR frames cannot be received anymore.
/linux/Documentation/devicetree/bindings/media/xilinx/
H A Dvideo.txt1 DT bindings for Xilinx video IP cores
4 Xilinx video IP cores process video streams by acting as video sinks and/or
10 cores are represented as defined in ../video-interfaces.txt.
18 The following properties are common to all Xilinx video IP cores.
21 AXI bus between video IP cores, using its VF code as defined in "AXI4-Stream
H A Dxlnx,video.txt8 video IP cores. Each video IP core is represented as documented in video.txt
11 mappings between DMAs and the video IP cores.
/linux/Documentation/devicetree/bindings/bus/
H A Dbrcm,bus-axi.txt9 The cores on the AXI bus are automatically detected by bcma with the
12 BCM47xx/BCM53xx ARM SoCs. To assign IRQ numbers to the cores, provide
17 The top-level axi bus may contain children representing attached cores
19 detected (e.g. IRQ numbers). Also some of the cores may be responsible
/linux/Documentation/arch/x86/
H A Damd-hfi.rst16 architectural class and CPUs are comprised of cores of various efficiency and
17 power capabilities: performance-oriented *classic cores* and power-efficient
18 *dense cores*. As such, power management strategies must be designed to
26 sending background threads to the dense cores while sending high priority
27 threads to the classic cores. From a performance perspective, sending
28 background threads to dense cores can free up power headroom and allow the
29 classic cores to optimally service demanding threads. Furthermore, the area
30 optimized nature of the dense cores allows for an increasing number of
31 physical cores. This improved core density will have positive multithreaded
/linux/arch/riscv/
H A DKconfig.errata9 here if your platform uses Andes CPU cores.
20 non-standard handling on non-coherent operations on Andes cores.
30 here if your platform uses MIPS CPU cores.
53 here if your platform uses SiFive CPU cores.
104 here if your platform uses T-HEAD CPU cores.
137 The T-Head C9xx cores implement a PMU overflow extension very
150 The T-Head C9xx cores have a vulnerability in the xtheadvector
/linux/drivers/bcma/
H A Dmain.c92 list_for_each_entry(core, &bus->cores, list) { in bcma_find_core_unit()
272 INIT_LIST_HEAD(&bus->cores); in bcma_init_bus()
296 list_for_each_entry(core, &bus->cores, list) { in bcma_register_devices()
372 list_for_each_entry_safe(core, tmp, &bus->cores, list) { in bcma_unregister_cores()
382 list_for_each_entry_safe(core, tmp, &bus->cores, list) { in bcma_unregister_cores()
418 list_for_each_entry(core, &bus->cores, list) { in bcma_bus_register()
543 list_for_each_entry(core, &bus->cores, list) { in bcma_bus_suspend()
564 list_for_each_entry(core, &bus->cores, list) { in bcma_bus_resume()
H A Ddriver_mips.c122 list_for_each_entry(core, &bus->cores, list) { in bcma_core_mips_set_irq()
172 list_for_each_entry(core, &bus->cores, list) { in bcma_core_mips_dump_irq()
343 list_for_each_entry(core, &bus->cores, list) { in bcma_core_mips_init()
/linux/sound/soc/sof/
H A Dipc4-mtrace.c113 struct sof_mtrace_core_data cores[]; member
403 debugfs_create_file(dfs_name, 0444, dfs_root, &priv->cores[i], in mtrace_debugfs_create()
483 struct sof_mtrace_core_data *core_data = &priv->cores[i]; in ipc4_mtrace_disable()
519 core_data = &priv->cores[core]; in sof_mtrace_find_core_slots()
556 priv = devm_kzalloc(sdev->dev, struct_size(priv, cores, sdev->num_cores), in ipc4_mtrace_init()
570 struct sof_mtrace_core_data *core_data = &priv->cores[i]; in ipc4_mtrace_init()
625 core_data = &priv->cores[core]; in sof_ipc4_mtrace_update_pos()
/linux/arch/arm/boot/dts/arm/
H A Dvexpress-v2p-ca15-tc1.dts199 regulator-cores {
210 amp-cores {
211 /* Total current for the two cores */
224 power-cores {
H A Dvexpress-v2p-ca15_a7.dts360 /* Total current for the two A15 cores */
367 /* Total current for the three A7 cores */
381 /* Total power for the two A15 cores */
388 /* Total power for the three A7 cores */
395 /* Total energy for the two A15 cores */
402 /* Total energy for the three A7 cores */
/linux/Documentation/ABI/testing/
H A Dsysfs-bus-bcma14 There are a few types of BCMA cores, they can be identified by
22 BCMA cores of the same type can still slightly differ depending
/linux/Documentation/admin-guide/device-mapper/
H A Dunstriped.rst85 Intel NVMe drives contain two cores on the physical device.
88 in a 256k stripe across the two cores::
100 are striped across the two cores. When we unstripe this hardware RAID 0
113 unstriped on top of Intel NVMe device that has 2 cores
/linux/Documentation/admin-guide/perf/
H A Darm_dsu_pmu.rst5 ARM DynamIQ Shared Unit integrates one or more cores with an L3 memory system,
11 cores connected to the same DSU. Like most of the other uncore PMUs, DSU
/linux/arch/arm/boot/dts/samsung/
H A Dexynos5422-odroidxu3-lite.dts39 * than Odroid XU3/XU4 boards: 1.8 GHz for A15 cores & 1.3 GHz for A7 cores.
/linux/drivers/cpuidle/
H A DKconfig.arm56 define different C-states for little and big cores through the
131 CPU and L2 cores. It interface with various system drivers to put
132 the cores in low power modes.
/linux/arch/arc/
H A DKconfig104 The original ARC ISA of ARC600/700 cores
110 ISA for the Next Generation ARC-HS cores
139 - SMP configurations of up to 4 cores with coherency
184 In SMP configuration cores can be configured as Halt-on-reset
197 This IP block enables SMP in ARC-HS38 cores.
430 On HS cores, taken interrupt auto saves the regfile on stack.
437 On HS cores, loop buffer (LPB) is programmable in runtime and can
483 ARC cores with 40 bit Physical Addressing support
/linux/drivers/net/can/esd/
H A Desdacc.c144 void acc_init_bm_ptr(struct acc_ov *ov, struct acc_core *cores, const void *mem) in acc_init_bm_ptr() argument
166 struct acc_core *core = &cores[u]; in acc_init_bm_ptr()
716 irqreturn_t acc_card_interrupt(struct acc_ov *ov, struct acc_core *cores) in acc_card_interrupt() argument
733 struct acc_core *core = &cores[i]; in acc_card_interrupt()
757 struct acc_core *core = &cores[i]; in acc_card_interrupt()
/linux/tools/perf/tests/
H A Dmake32 …cores := $(shell (getconf _NPROCESSORS_ONLN || grep -E -c '^processor|^CPU[0-9]' /proc/cpuinfo) 2>…
33 ifeq ($(cores),0)
34 cores := 1
37 cores=$(JOBS)
39 PARALLEL_OPT="-j$(cores)"
/linux/Documentation/admin-guide/pm/
H A Dintel-speed-select.rst325 power among cores when there is a power constrained scenario. This defines a
673 also adjusts the priority of cores using Intel(R) Speed Select Technology Core
732 to cores based on the priority. By using this feature, some cores can be
734 the cost of lower or no turbo frequency on the low priority cores.
855 high-priority-cores-count:2
860 high-priority-cores-count:4
865 high-priority-cores-count:6
875 two high priority cores. If only two high priority cores are set, then max.
876 turbo frequency on those cores can be increased to 3200 MHz. This is 100 MHz
877 more than the base turbo capability for all cores.
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/linux/Documentation/devicetree/bindings/arc/
H A Daxs103.txt5 HS38x cores.
/linux/Documentation/admin-guide/hw-vuln/
H A Dl1d_flush.rst63 cores or by disabling SMT. See the relevant chapter in the L1TF mitigation
67 affinity is limited to cores running in non-SMT mode. If a task which
/linux/drivers/irqchip/
H A Dirq-loongson-eiointc.c200 int i, bit, cores, index, node; in eiointc_router_init() local
220 cores = CORES_PER_EIO_NODE; in eiointc_router_init()
222 cores = CORES_PER_VEIO_NODE; in eiointc_router_init()
224 if ((cpu_logical_map(cpu) % cores) == 0) { in eiointc_router_init()
/linux/arch/arm/boot/dts/intel/socfpga/
H A Dsocfpga_arria5.dtsi7 /* First 4KB has trampoline code for secondary cores. */

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