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/linux/Documentation/admin-guide/
H A Dlockup-watchdogs.rst67 By default, the watchdog runs on all online cores. However, on a
69 on the housekeeping cores, not the cores specified in the "nohz_full"
71 the "nohz_full" cores, we would have to run timer ticks to activate
73 from protecting the user code on those cores from the kernel.
74 Of course, disabling it by default on the nohz_full cores means that
75 when those cores do enter the kernel, by default we will not be
77 to continue to run on the housekeeping (non-tickless) cores means
78 that we will continue to detect lockups properly on those cores.
80 In either case, the set of cores excluded from running the watchdog
82 nohz_full cores, this may be useful for debugging a case where the
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/linux/drivers/gpu/drm/nouveau/dispnv50/
H A Dcore.c44 } cores[] = { in nv50_core_new() local
66 cid = nvif_mclass(&disp->disp->object, cores); in nv50_core_new()
72 return cores[cid].new(drm, cores[cid].oclass, pcore); in nv50_core_new()
/linux/Documentation/devicetree/bindings/timer/
H A Dsnps,arc-timer.txt4 - Two identical copies TIMER0 and TIMER1 exist in ARC cores and historically
5 TIMER0 used as clockevent provider (true for all ARC cores)
12 (16 for ARCHS cores, 3 for ARC700 cores)
/linux/Documentation/networking/device_drivers/can/freescale/
H A Dflexcan.rst13 For most flexcan IP cores the driver supports 2 RX modes:
18 The older flexcan cores (integrated into the i.MX25, i.MX28, i.MX35
28 cores come up in a mode where RTR reception is possible.
39 On some IP cores the controller cannot receive RTR frames in the
45 Waive ability to receive RTR frames. (not supported on all IP cores)
48 some IP cores RTR frames cannot be received anymore.
/linux/Documentation/devicetree/bindings/media/xilinx/
H A Dvideo.txt1 DT bindings for Xilinx video IP cores
4 Xilinx video IP cores process video streams by acting as video sinks and/or
10 cores are represented as defined in ../video-interfaces.txt.
18 The following properties are common to all Xilinx video IP cores.
21 AXI bus between video IP cores, using its VF code as defined in "AXI4-Stream
H A Dxlnx,video.txt8 video IP cores. Each video IP core is represented as documented in video.txt
11 mappings between DMAs and the video IP cores.
/linux/drivers/net/can/esd/
H A Desd_402_pci-core.c50 struct acc_core *cores; member
103 irq_status = acc_card_interrupt(&card->ov, card->cores); in pci402_interrupt()
195 card->cores = devm_kcalloc(&pdev->dev, card->ov.active_cores, in pci402_init_card()
197 if (!card->cores) in pci402_init_card()
286 acc_init_bm_ptr(&card->ov, card->cores, card->dma_buf); in pci402_init_dma()
316 struct acc_core *core = &card->cores[i]; in pci402_finish_dma()
343 struct acc_core *core = &card->cores[i]; in pci402_init_cores()
404 pci402_unregister_core(&card->cores[i]); in pci402_init_cores()
415 pci402_unregister_core(&card->cores[i]); in pci402_finish_cores()
/linux/Documentation/devicetree/bindings/bus/
H A Dbrcm,bus-axi.txt9 The cores on the AXI bus are automatically detected by bcma with the
12 BCM47xx/BCM53xx ARM SoCs. To assign IRQ numbers to the cores, provide
17 The top-level axi bus may contain children representing attached cores
19 detected (e.g. IRQ numbers). Also some of the cores may be responsible
/linux/arch/x86/mm/
H A Damdtopology.c58 unsigned int numnodes, cores, apicid; in amd_numa_init() local
163 cores = topology_get_domain_size(TOPO_CORE_DOMAIN); in amd_numa_init()
170 for (j = 0; j < cores; j++, apicid++) in amd_numa_init()
/linux/drivers/bcma/
H A Dmain.c92 list_for_each_entry(core, &bus->cores, list) { in bcma_find_core_unit()
272 INIT_LIST_HEAD(&bus->cores); in bcma_init_bus()
296 list_for_each_entry(core, &bus->cores, list) { in bcma_register_devices()
366 list_for_each_entry_safe(core, tmp, &bus->cores, list) { in bcma_unregister_cores()
376 list_for_each_entry_safe(core, tmp, &bus->cores, list) { in bcma_unregister_cores()
412 list_for_each_entry(core, &bus->cores, list) { in bcma_bus_register()
537 list_for_each_entry(core, &bus->cores, list) { in bcma_bus_suspend()
558 list_for_each_entry(core, &bus->cores, list) { in bcma_bus_resume()
H A Ddriver_mips.c122 list_for_each_entry(core, &bus->cores, list) { in bcma_core_mips_set_irq()
172 list_for_each_entry(core, &bus->cores, list) { in bcma_core_mips_dump_irq()
343 list_for_each_entry(core, &bus->cores, list) { in bcma_core_mips_init()
/linux/sound/soc/sof/
H A Dipc4-mtrace.c113 struct sof_mtrace_core_data cores[]; member
403 debugfs_create_file(dfs_name, 0444, dfs_root, &priv->cores[i], in mtrace_debugfs_create()
483 struct sof_mtrace_core_data *core_data = &priv->cores[i]; in ipc4_mtrace_disable()
519 core_data = &priv->cores[core]; in sof_mtrace_find_core_slots()
556 priv = devm_kzalloc(sdev->dev, struct_size(priv, cores, sdev->num_cores), in ipc4_mtrace_init()
570 struct sof_mtrace_core_data *core_data = &priv->cores[i]; in ipc4_mtrace_init()
625 core_data = &priv->cores[core]; in sof_ipc4_mtrace_update_pos()
/linux/drivers/gpu/drm/v3d/
H A Dv3d_irq.c238 for (core = 0; core < v3d->cores; core++) in v3d_irq_init()
283 for (core = 0; core < v3d->cores; core++) { in v3d_irq_enable()
298 for (core = 0; core < v3d->cores; core++) in v3d_irq_disable()
303 for (core = 0; core < v3d->cores; core++) in v3d_irq_disable()
H A Dv3d_debugfs.c119 for (core = 0; core < v3d->cores; core++) { in v3d_v3d_debugfs_regs()
149 u32 ident0, ident1, ident2, ident3, cores; in v3d_v3d_debugfs_ident() local
156 cores = V3D_GET_FIELD(ident1, V3D_HUB_IDENT1_NCORES); in v3d_v3d_debugfs_ident()
177 for (core = 0; core < cores; core++) { in v3d_v3d_debugfs_ident()
/linux/arch/arm/boot/dts/arm/
H A Dvexpress-v2p-ca15-tc1.dts199 regulator-cores {
210 amp-cores {
211 /* Total current for the two cores */
224 power-cores {
H A Dvexpress-v2p-ca15_a7.dts360 /* Total current for the two A15 cores */
367 /* Total current for the three A7 cores */
381 /* Total power for the two A15 cores */
388 /* Total power for the three A7 cores */
395 /* Total energy for the two A15 cores */
402 /* Total energy for the three A7 cores */
/linux/Documentation/admin-guide/device-mapper/
H A Dunstriped.rst85 Intel NVMe drives contain two cores on the physical device.
88 in a 256k stripe across the two cores::
100 are striped across the two cores. When we unstripe this hardware RAID 0
113 unstriped on top of Intel NVMe device that has 2 cores
/linux/Documentation/ABI/testing/
H A Dsysfs-bus-bcma14 There are a few types of BCMA cores, they can be identified by
22 BCMA cores of the same type can still slightly differ depending
/linux/drivers/net/wireless/intel/iwlwifi/tests/
H A Ddevinfo.c19 di->cores); in iwl_pci_print_dev_info()
34 di->no_160, di->cores, di->rf_step); in devinfo_table_order()
/linux/drivers/soc/tegra/
H A DKconfig85 the Tegra210 has four Cortex-A57 cores paired with four Cortex-A53
86 cores in a switched configuration. It features a GPU of the Maxwell
88 and providing 256 CUDA cores. It supports hardware-accelerated en-
106 combination of Denver and Cortex-A57 CPU cores and a GPU based on
/linux/Documentation/devicetree/bindings/
H A Dxilinx.txt1 d) Xilinx IP cores
3 The Xilinx EDK toolchain ships with a set of IP cores (devices) for use
14 device drivers how the IP cores are configured, but it requires the kernel
20 properties of the device node. In general, device nodes for IP-cores
89 That covers the general approach to binding xilinx IP cores into the
/linux/Documentation/admin-guide/perf/
H A Darm_dsu_pmu.rst5 ARM DynamIQ Shared Unit integrates one or more cores with an L3 memory system,
11 cores connected to the same DSU. Like most of the other uncore PMUs, DSU
/linux/arch/arm/boot/dts/samsung/
H A Dexynos5422-odroidxu3-lite.dts39 * than Odroid XU3/XU4 boards: 1.8 GHz for A15 cores & 1.3 GHz for A7 cores.
/linux/drivers/cpuidle/
H A DKconfig.arm56 define different C-states for little and big cores through the
131 CPU and L2 cores. It interface with various system drivers to put
132 the cores in low power modes.
/linux/arch/arc/
H A DKconfig104 The original ARC ISA of ARC600/700 cores
110 ISA for the Next Generation ARC-HS cores
139 - SMP configurations of up to 4 cores with coherency
184 In SMP configuration cores can be configured as Halt-on-reset
197 This IP block enables SMP in ARC-HS38 cores.
430 On HS cores, taken interrupt auto saves the regfile on stack.
437 On HS cores, loop buffer (LPB) is programmable in runtime and can
483 ARC cores with 40 bit Physical Addressing support

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