Searched refs:component_reg_phys (Results 1 – 5 of 5) sorted by relevance
752 port->component_reg_phys = CXL_RESOURCE_NONE; in cxl_port_alloc()764 resource_size_t component_reg_phys) in cxl_setup_comp_regs() argument769 .resource = component_reg_phys, in cxl_setup_comp_regs()772 if (component_reg_phys == CXL_RESOURCE_NONE) in cxl_setup_comp_regs()782 resource_size_t component_reg_phys) in cxl_port_setup_regs() argument787 component_reg_phys); in cxl_port_setup_regs()791 resource_size_t component_reg_phys) in cxl_dport_setup_regs() argument804 component_reg_phys); in cxl_dport_setup_regs()844 resource_size_t component_reg_phys, in cxl_port_add() argument871 port->component_reg_phys = component_reg_phys; in cxl_port_add()[all …]
580 resource_size_t component_reg_phys; in __rcrb_to_component() local623 component_reg_phys = bar0 & PCI_BASE_ADDRESS_MEM_MASK; in __rcrb_to_component()625 component_reg_phys |= ((u64)bar1) << 32; in __rcrb_to_component()627 if (!component_reg_phys) in __rcrb_to_component()631 if (!IS_ALIGNED(component_reg_phys, CXL_COMPONENT_REG_BLOCK_SIZE)) in __rcrb_to_component()634 return component_reg_phys; in __rcrb_to_component()
713 resource_size_t component_reg_phys; in add_host_bridge_uport() local742 component_reg_phys = ctx.base; in add_host_bridge_uport()743 if (component_reg_phys != CXL_RESOURCE_NONE) in add_host_bridge_uport()745 ctx.uid, &component_reg_phys); in add_host_bridge_uport()751 port = devm_cxl_add_port(host, bridge, component_reg_phys, dport); in add_host_bridge_uport()
642 resource_size_t component_reg_phys; member779 resource_size_t component_reg_phys,801 resource_size_t component_reg_phys);
481 resource_size_t component_reg_phys; in cxl_rcrb_get_comp_regs() local493 component_reg_phys = cxl_rcd_component_reg_phys(&pdev->dev, dport); in cxl_rcrb_get_comp_regs()494 if (component_reg_phys == CXL_RESOURCE_NONE) in cxl_rcrb_get_comp_regs()497 map->resource = component_reg_phys; in cxl_rcrb_get_comp_regs()