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Searched refs:cntr_mask64 (Results 1 – 3 of 3) sorted by relevance

/linux/arch/x86/events/amd/
H A Dcore.c1335 .cntr_mask64 = GENMASK_ULL(AMD64_NUM_COUNTERS - 1, 0),
1434 x86_pmu.cntr_mask64 = GENMASK_ULL(AMD64_NUM_COUNTERS_CORE - 1, 0); in amd_core_pmu_init()
1444 x86_pmu.cntr_mask64 = GENMASK_ULL(ebx.split.num_core_pmc - 1, 0); in amd_core_pmu_init()
1446 amd_pmu_global_cntr_mask = x86_pmu.cntr_mask64; in amd_core_pmu_init()
/linux/arch/x86/events/
H A Dperf_event.h749 u64 cntr_mask64; member
862 u64 cntr_mask64; member
1322 return hweight64(hybrid(pmu, cntr_mask64)); in x86_pmu_num_counters()
1327 return fls64(hybrid(pmu, cntr_mask64)); in x86_pmu_max_num_counters()
/linux/arch/x86/events/intel/
H A Dcore.c6147 u64 cntr_mask = hybrid(pmu, cntr_mask64); in intel_pmu_check_event_constraints_all()
6228 hybrid(pmu, cntr_mask64) = eax; in update_pmu_cap_from_perfmonext()
6288 intel_pmu_check_counters_mask(&pmu->cntr_mask64, &pmu->fixed_cntr_mask64, in intel_pmu_check_hybrid_pmus()
6290 pmu->pebs_events_mask = intel_pmu_pebs_mask(pmu->cntr_mask64); in intel_pmu_check_hybrid_pmus()
6292 __EVENT_CONSTRAINT(0, pmu->cntr_mask64, in intel_pmu_check_hybrid_pmus()
7736 pmu->cntr_mask64 = x86_pmu.cntr_mask64; in intel_pmu_init_hybrid()
7738 pmu->pebs_events_mask = intel_pmu_pebs_mask(pmu->cntr_mask64); in intel_pmu_init_hybrid()
7741 __EVENT_CONSTRAINT(0, pmu->cntr_mask64, in intel_pmu_init_hybrid()
7951 x86_pmu.cntr_mask64 = GENMASK_ULL(eax.split.num_counters - 1, 0); in intel_pmu_init()
7958 x86_pmu.pebs_events_mask = intel_pmu_pebs_mask(x86_pmu.cntr_mask64); in intel_pmu_init()
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