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Searched refs:cntr_mask64 (Results 1 – 3 of 3) sorted by relevance

/linux/arch/x86/events/intel/
H A Dcore.c5841 u64 cntr_mask = hybrid(pmu, cntr_mask64); in intel_pmu_check_event_constraints_all()
5916 hybrid(pmu, cntr_mask64) = eax; in update_pmu_cap()
5962 intel_pmu_check_counters_mask(&pmu->cntr_mask64, &pmu->fixed_cntr_mask64, in intel_pmu_check_hybrid_pmus()
5964 pmu->pebs_events_mask = intel_pmu_pebs_mask(pmu->cntr_mask64); in intel_pmu_check_hybrid_pmus()
5966 __EVENT_CONSTRAINT(0, pmu->cntr_mask64, in intel_pmu_check_hybrid_pmus()
7407 pmu->cntr_mask64 = x86_pmu.cntr_mask64; in intel_pmu_init_hybrid()
7409 pmu->pebs_events_mask = intel_pmu_pebs_mask(pmu->cntr_mask64); in intel_pmu_init_hybrid()
7412 __EVENT_CONSTRAINT(0, pmu->cntr_mask64, in intel_pmu_init_hybrid()
7573 x86_pmu.cntr_mask64 = GENMASK_ULL(eax.split.num_counters - 1, 0); in intel_pmu_init()
7580 x86_pmu.pebs_events_mask = intel_pmu_pebs_mask(x86_pmu.cntr_mask64); in intel_pmu_init()
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/linux/arch/x86/events/
H A Dperf_event.h741 u64 cntr_mask64; member
854 u64 cntr_mask64; member
1313 return hweight64(hybrid(pmu, cntr_mask64)); in x86_pmu_num_counters()
1318 return fls64(hybrid(pmu, cntr_mask64)); in x86_pmu_max_num_counters()
H A Dcore.c207 u64 cntr_mask = x86_pmu.cntr_mask64; in get_possible_counter_mask()
214 cntr_mask |= x86_pmu.hybrid_pmu[i].cntr_mask64; in get_possible_counter_mask()
2122 pr_info("... generic bitmap: %016llx\n", hybrid(pmu, cntr_mask64)); in x86_pmu_show_pmu_cap()
2176 x86_pmu.intel_ctrl = x86_pmu.cntr_mask64; in init_hw_perf_events()
2185 __EVENT_CONSTRAINT(0, x86_pmu.cntr_mask64, in init_hw_perf_events()