Searched refs:cntr_mask (Results 1 – 4 of 4) sorted by relevance
| /linux/arch/x86/events/ |
| H A D | rapl.c | 143 unsigned int cntr_mask; member
411 if (!(rapl_pmus->cntr_mask & (1 << bit))) in rapl_pmu_event_init()
658 int num_counters = hweight32(rapl_pmus_pkg->cntr_mask); in rapl_advertise()
661 num_counters += hweight32(rapl_pmus_core->cntr_mask); in rapl_advertise()
667 if (rapl_pmus_pkg->cntr_mask & (1 << i)) { in rapl_advertise()
673 if (rapl_pmus_core && (rapl_pmus_core->cntr_mask & (1 << PERF_RAPL_CORE))) in rapl_advertise()
917 rapl_pmus_pkg->cntr_mask = perf_msr_probe(rapl_model->rapl_pkg_msrs, in rapl_pmu_init()
934 rapl_pmus_core->cntr_mask = perf_msr_probe(rapl_model->rapl_core_msrs, in rapl_pmu_init()
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| /linux/arch/x86/events/amd/ |
| H A D | core.c | 439 for_each_set_bit(i, x86_pmu.cntr_mask, X86_PMC_IDX_MAX) { in __amd_put_nb_event_constraints()
551 for_each_set_bit(i, x86_pmu.cntr_mask, X86_PMC_IDX_MAX) { in amd_alloc_nb()
744 for_each_set_bit(idx, x86_pmu.cntr_mask, X86_PMC_IDX_MAX) { in amd_pmu_check_overflow()
762 for_each_set_bit(idx, x86_pmu.cntr_mask, X86_PMC_IDX_MAX) { in __amd_pmu_enable_all()
997 for_each_set_bit(idx, x86_pmu.cntr_mask, X86_PMC_IDX_MAX) { in amd_pmu_v2_handle_irq()
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| /linux/drivers/perf/ |
| H A D | arm_pmu.c | 756 for_each_set_bit(idx, armpmu->cntr_mask, ARMPMU_MAX_HWEVENTS) { in cpu_pm_pmu_setup()
950 pmu->name, bitmap_weight(pmu->cntr_mask, ARMPMU_MAX_HWEVENTS), in armpmu_register()
951 ARMPMU_MAX_HWEVENTS, &pmu->cntr_mask, in armpmu_register()
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| /linux/arch/x86/events/intel/ |
| H A D | core.c | 3699 unsigned long *cntr_mask = hybrid(cpuc->pmu, cntr_mask); in intel_pmu_reset() local
3704 if (!*(u64 *)cntr_mask) in intel_pmu_reset()
3711 for_each_set_bit(idx, cntr_mask, INTEL_PMC_MAX_GENERIC) { in intel_pmu_reset()
4955 u64 cntr_mask = hybrid(event->pmu, intel_ctrl) & in intel_pmu_hw_config() local
4959 if (cntr_mask != pebs_mask) in intel_pmu_hw_config()
5359 for_each_set_bit(idx, x86_pmu.cntr_mask, X86_PMC_IDX_MAX) { in core_guest_get_msrs()
5392 for_each_set_bit(idx, x86_pmu.cntr_mask, X86_PMC_IDX_MAX) { in core_pmu_enable_all()
5954 static void intel_pmu_check_counters_mask(u64 *cntr_mask, in intel_pmu_check_counters_mask() argument
5960 bit = fls64(*cntr_mask); in intel_pmu_check_counters_mask()
5964 *cntr_mask &= GENMASK_ULL(INTEL_PMC_MAX_GENERIC - 1, 0); in intel_pmu_check_counters_mask()
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