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Searched refs:cntr_mask (Results 1 – 5 of 5) sorted by relevance

/linux/arch/x86/events/
H A Dcore.c204 u64 cntr_mask = x86_pmu.cntr_mask64; in get_possible_counter_mask() local
208 return cntr_mask; in get_possible_counter_mask()
211 cntr_mask |= x86_pmu.hybrid_pmu[i].cntr_mask64; in get_possible_counter_mask()
213 return cntr_mask; in get_possible_counter_mask()
218 u64 cntr_mask = get_possible_counter_mask(); in reserve_pmc_hardware() local
221 for_each_set_bit(i, (unsigned long *)&cntr_mask, X86_PMC_IDX_MAX) { in reserve_pmc_hardware()
226 for_each_set_bit(i, (unsigned long *)&cntr_mask, X86_PMC_IDX_MAX) { in reserve_pmc_hardware()
235 for_each_set_bit(i, (unsigned long *)&cntr_mask, end) in reserve_pmc_hardware()
241 for_each_set_bit(i, (unsigned long *)&cntr_mask, end) in reserve_pmc_hardware()
249 u64 cntr_mask = get_possible_counter_mask(); in release_pmc_hardware() local
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H A Dperf_event.h731 unsigned long cntr_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)]; member
844 unsigned long cntr_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)]; member
1225 bool check_hw_exists(struct pmu *pmu, unsigned long *cntr_mask,
1819 static inline u64 intel_pmu_pebs_mask(u64 cntr_mask) in intel_pmu_pebs_mask() argument
1821 return MAX_PEBS_EVENTS_MASK & cntr_mask; in intel_pmu_pebs_mask()
/linux/arch/x86/events/intel/
H A Dcore.c3185 unsigned long *cntr_mask = hybrid(cpuc->pmu, cntr_mask); in intel_pmu_reset() local
3190 if (!*(u64 *)cntr_mask) in intel_pmu_reset()
3197 for_each_set_bit(idx, cntr_mask, INTEL_PMC_MAX_GENERIC) { in intel_pmu_reset()
4405 u64 cntr_mask = hybrid(event->pmu, intel_ctrl) & in intel_pmu_hw_config() local
4409 if (cntr_mask != pebs_mask) in intel_pmu_hw_config()
4807 for_each_set_bit(idx, x86_pmu.cntr_mask, X86_PMC_IDX_MAX) { in core_guest_get_msrs()
4840 for_each_set_bit(idx, x86_pmu.cntr_mask, X86_PMC_IDX_MAX) { in core_pmu_enable_all()
5395 static void intel_pmu_check_counters_mask(u64 *cntr_mask, in intel_pmu_check_counters_mask() argument
5401 bit = fls64(*cntr_mask); in intel_pmu_check_counters_mask()
5405 *cntr_mask &= GENMASK_ULL(INTEL_PMC_MAX_GENERIC - 1, 0); in intel_pmu_check_counters_mask()
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H A Dds.c1536 u64 cntr_mask; in intel_get_arch_pebs_data_config() local
1543 cntr_mask = (PEBS_DATACFG_CNTR_MASK << PEBS_DATACFG_CNTR_SHIFT) | in intel_get_arch_pebs_data_config()
1546 pebs_data_cfg |= cpuc->pebs_data_cfg & cntr_mask; in intel_get_arch_pebs_data_config()
/linux/arch/arm64/kvm/
H A Dpmu-emul.c1025 return bitmap_weight(arm_pmu->cntr_mask, ARMV8_PMU_MAX_GENERAL_COUNTERS); in kvm_arm_pmu_get_max_counters()