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Searched refs:cntr_mask (Results 1 – 6 of 6) sorted by relevance

/linux/arch/x86/events/
H A Drapl.c143 unsigned int cntr_mask; member
411 if (!(rapl_pmus->cntr_mask & (1 << bit))) in rapl_pmu_event_init()
658 int num_counters = hweight32(rapl_pmus_pkg->cntr_mask); in rapl_advertise()
661 num_counters += hweight32(rapl_pmus_core->cntr_mask); in rapl_advertise()
667 if (rapl_pmus_pkg->cntr_mask & (1 << i)) { in rapl_advertise()
673 if (rapl_pmus_core && (rapl_pmus_core->cntr_mask & (1 << PERF_RAPL_CORE))) in rapl_advertise()
917 rapl_pmus_pkg->cntr_mask = perf_msr_probe(rapl_model->rapl_pkg_msrs, in rapl_pmu_init()
934 rapl_pmus_core->cntr_mask = perf_msr_probe(rapl_model->rapl_core_msrs, in rapl_pmu_init()
H A Dcore.c207 u64 cntr_mask = x86_pmu.cntr_mask64; in get_possible_counter_mask() local
211 return cntr_mask; in get_possible_counter_mask()
214 cntr_mask |= x86_pmu.hybrid_pmu[i].cntr_mask64; in get_possible_counter_mask()
216 return cntr_mask; in get_possible_counter_mask()
221 u64 cntr_mask = get_possible_counter_mask(); in reserve_pmc_hardware() local
224 for_each_set_bit(i, (unsigned long *)&cntr_mask, X86_PMC_IDX_MAX) { in reserve_pmc_hardware()
229 for_each_set_bit(i, (unsigned long *)&cntr_mask, X86_PMC_IDX_MAX) { in reserve_pmc_hardware()
238 for_each_set_bit(i, (unsigned long *)&cntr_mask, end) in reserve_pmc_hardware()
244 for_each_set_bit(i, (unsigned long *)&cntr_mask, end) in reserve_pmc_hardware()
252 u64 cntr_mask = get_possible_counter_mask(); in release_pmc_hardware() local
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H A Dperf_event.h752 unsigned long cntr_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)]; member
865 unsigned long cntr_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)]; member
1247 bool check_hw_exists(struct pmu *pmu, unsigned long *cntr_mask,
1855 static inline u64 intel_pmu_pebs_mask(u64 cntr_mask) in intel_pmu_pebs_mask() argument
1857 return MAX_PEBS_EVENTS_MASK & cntr_mask; in intel_pmu_pebs_mask()
/linux/arch/x86/events/intel/
H A Dcore.c3448 unsigned long *cntr_mask = hybrid(cpuc->pmu, cntr_mask); in intel_pmu_reset() local
3453 if (!*(u64 *)cntr_mask) in intel_pmu_reset()
3460 for_each_set_bit(idx, cntr_mask, INTEL_PMC_MAX_GENERIC) { in intel_pmu_reset()
4706 u64 cntr_mask = hybrid(event->pmu, intel_ctrl) & in intel_pmu_hw_config() local
4710 if (cntr_mask != pebs_mask) in intel_pmu_hw_config()
5108 for_each_set_bit(idx, x86_pmu.cntr_mask, X86_PMC_IDX_MAX) { in core_guest_get_msrs()
5141 for_each_set_bit(idx, x86_pmu.cntr_mask, X86_PMC_IDX_MAX) { in core_pmu_enable_all()
5696 static void intel_pmu_check_counters_mask(u64 *cntr_mask, in intel_pmu_check_counters_mask() argument
5702 bit = fls64(*cntr_mask); in intel_pmu_check_counters_mask()
5706 *cntr_mask &= GENMASK_ULL(INTEL_PMC_MAX_GENERIC - 1, 0); in intel_pmu_check_counters_mask()
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H A Dds.c1800 u64 cntr_mask; in intel_get_arch_pebs_data_config() local
1807 cntr_mask = (PEBS_DATACFG_CNTR_MASK << PEBS_DATACFG_CNTR_SHIFT) | in intel_get_arch_pebs_data_config()
1810 pebs_data_cfg |= cpuc->pebs_data_cfg & cntr_mask; in intel_get_arch_pebs_data_config()
/linux/drivers/perf/
H A Darm_pmu.c756 for_each_set_bit(idx, armpmu->cntr_mask, ARMPMU_MAX_HWEVENTS) { in cpu_pm_pmu_setup()
945 pmu->name, bitmap_weight(pmu->cntr_mask, ARMPMU_MAX_HWEVENTS), in armpmu_register()
946 ARMPMU_MAX_HWEVENTS, &pmu->cntr_mask, in armpmu_register()