Searched refs:cmrr (Results 1 – 4 of 4) sorted by relevance
154 crtc_state->cmrr.cmrr_n = mul_u32_u32(desired_refresh_rate * adjusted_mode->crtc_htotal, in cmrr_get_vtotal()157 crtc_state->cmrr.cmrr_n); in cmrr_get_vtotal()159 crtc_state->cmrr.cmrr_m = do_div(adjusted_pixel_rate, crtc_state->cmrr.cmrr_n); in cmrr_get_vtotal()226 crtc_state->cmrr.enable = true; in intel_vrr_compute_config()300 if (crtc_state->cmrr.enable) { in intel_vrr_set_transcoder_timings()302 upper_32_bits(crtc_state->cmrr.cmrr_m)); in intel_vrr_set_transcoder_timings()304 lower_32_bits(crtc_state->cmrr.cmrr_m)); in intel_vrr_set_transcoder_timings()306 upper_32_bits(crtc_state->cmrr.cmrr_n)); in intel_vrr_set_transcoder_timings()308 lower_32_bits(crtc_state->cmrr.cmrr_n)); in intel_vrr_set_transcoder_timings()361 if (crtc_state->cmrr.enable) { in intel_vrr_enable()[all …]
1117 return old_crtc_state->cmrr.cmrr_m != new_crtc_state->cmrr.cmrr_m || in cmrr_params_changed()1118 old_crtc_state->cmrr.cmrr_n != new_crtc_state->cmrr.cmrr_n; in cmrr_params_changed()5762 PIPE_CONF_CHECK_LLI(cmrr.cmrr_m); in intel_pipe_config_compare()5763 PIPE_CONF_CHECK_LLI(cmrr.cmrr_n); in intel_pipe_config_compare()5764 PIPE_CONF_CHECK_BOOL(cmrr.enable); in intel_pipe_config_compare()
1295 } cmrr; member
2786 if (crtc_state->cmrr.enable) { in intel_dp_compute_as_sdp()