Searched refs:cmdr (Results 1 – 6 of 6) sorted by relevance
256 u32 cmdr; in dw_mci_prepare_command() local259 cmdr = cmd->opcode; in dw_mci_prepare_command()266 cmdr |= SDMMC_CMD_STOP; in dw_mci_prepare_command()268 cmdr |= SDMMC_CMD_PRV_DAT_WAIT; in dw_mci_prepare_command()274 cmdr |= SDMMC_CMD_VOLT_SWITCH; in dw_mci_prepare_command()300 cmdr |= SDMMC_CMD_RESP_EXP; in dw_mci_prepare_command()302 cmdr |= SDMMC_CMD_RESP_LONG; in dw_mci_prepare_command()306 cmdr |= SDMMC_CMD_RESP_CRC; in dw_mci_prepare_command()309 cmdr |= SDMMC_CMD_DAT_EXP; in dw_mci_prepare_command()311 cmdr |= SDMMC_CMD_DAT_WR; in dw_mci_prepare_command()[all …]
792 u32 cmdr; in atmci_prepare_command() local796 cmdr = ATMCI_CMDR_CMDNB(cmd->opcode); in atmci_prepare_command()800 cmdr |= ATMCI_CMDR_RSPTYP_136BIT; in atmci_prepare_command()802 cmdr |= ATMCI_CMDR_RSPTYP_48BIT; in atmci_prepare_command()810 cmdr |= ATMCI_CMDR_MAXLAT_64CYC; in atmci_prepare_command()813 cmdr |= ATMCI_CMDR_OPDCMD; in atmci_prepare_command()817 cmdr |= ATMCI_CMDR_START_XFER; in atmci_prepare_command()820 cmdr |= ATMCI_CMDR_SDIO_BLOCK; in atmci_prepare_command()823 cmdr |= ATMCI_CMDR_MULTI_BLOCK; in atmci_prepare_command()825 cmdr |= ATMCI_CMDR_BLOCK; in atmci_prepare_command()[all …]
214 u32 cmdr; member233 u32 cmdr; /* STM32 DMA Transfer Complete flag */ member684 dev_dbg(chan2dev(chan), "CMDR: 0x%08x\n\n", node->hwdesc->cmdr); in stm32_mdma_dump_hwdesc()710 hwdesc->cmdr = config->mask_data; in stm32_mdma_setup_hwdesc()824 hwdesc->cmdr = 0; in stm32_mdma_prep_slave_sg()1054 hwdesc->cmdr = 0; in stm32_mdma_prep_dma_memcpy()1170 stm32_mdma_write(dmadev, STM32_MDMA_CMDR(id), hwdesc->cmdr); in stm32_mdma_start_transfer()1311 chan->chan_config.mask_data = mdma_config->cmdr; in stm32_mdma_slave_config()
375 struct hifn_desc cmdr[HIFN_D_CMD_RSIZE + 1]; member870 dma->cmdr[i].p = __cpu_to_le32(dptr + in hifn_init_dma()877 dma->cmdr[HIFN_D_CMD_RSIZE].p = __cpu_to_le32(dptr + in hifn_init_dma()878 offsetof(struct hifn_dma, cmdr[0])); in hifn_init_dma()967 offsetof(struct hifn_dma, cmdr[0])); in hifn_init_registers()1192 dma->cmdr[dma->cmdi].l = __cpu_to_le32(cmd_len | HIFN_D_VALID | in hifn_setup_cmd_desc()1196 dma->cmdr[dma->cmdi].l = __cpu_to_le32( in hifn_setup_cmd_desc()1201 dma->cmdr[dma->cmdi - 1].l |= __cpu_to_le32(HIFN_D_VALID); in hifn_setup_cmd_desc()1735 if (dma->cmdr[i].l & __cpu_to_le32(HIFN_D_VALID)) in hifn_clear_rings()
43 u8 cmdr; /* Command Register */ member
135 void *cmdr; member965 hdr = udev->cmdr + cmd_head; in ring_insert_padding()1090 entry = udev->cmdr + cmd_head; in queue_cmd_ring()1182 entry = udev->cmdr + cmd_head; in queue_tmr_ring()1459 struct tcmu_cmd_entry *entry = udev->cmdr + udev->cmdr_last_cleaned; in tcmu_handle_completions()2227 udev->cmdr = (void *)mb + CMDR_OFF; in tcmu_configure_device()