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Searched refs:cmdq_reg (Results 1 – 8 of 8) sorted by relevance

/linux/drivers/gpu/drm/mediatek/
H A Dmtk_ddp_comp.c66 struct cmdq_client_reg cmdq_reg; member
70 struct cmdq_client_reg *cmdq_reg, void __iomem *regs, in mtk_ddp_write() argument
75 cmdq_pkt_write(cmdq_pkt, cmdq_reg->subsys, in mtk_ddp_write()
76 cmdq_reg->offset + offset, value); in mtk_ddp_write()
83 struct cmdq_client_reg *cmdq_reg, void __iomem *regs, in mtk_ddp_write_relaxed() argument
88 cmdq_pkt_write(cmdq_pkt, cmdq_reg->subsys, in mtk_ddp_write_relaxed()
89 cmdq_reg->offset + offset, value); in mtk_ddp_write_relaxed()
96 struct cmdq_client_reg *cmdq_reg, void __iomem *regs, in mtk_ddp_write_mask() argument
101 cmdq_pkt_write_mask(cmdq_pkt, cmdq_reg->subsys, in mtk_ddp_write_mask()
102 cmdq_reg->offset + offset, value, mask); in mtk_ddp_write_mask()
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H A Dmtk_disp_ccorr.c39 struct cmdq_client_reg cmdq_reg; member
63 mtk_ddp_write(cmdq_pkt, w << 16 | h, &ccorr->cmdq_reg, ccorr->regs, in mtk_ccorr_config()
65 mtk_ddp_write(cmdq_pkt, CCORR_ENGINE_EN, &ccorr->cmdq_reg, ccorr->regs, in mtk_ccorr_config()
104 &ccorr->cmdq_reg, ccorr->regs, DISP_CCORR_COEF_0); in mtk_ccorr_ctm_set()
106 &ccorr->cmdq_reg, ccorr->regs, DISP_CCORR_COEF_1); in mtk_ccorr_ctm_set()
108 &ccorr->cmdq_reg, ccorr->regs, DISP_CCORR_COEF_2); in mtk_ccorr_ctm_set()
110 &ccorr->cmdq_reg, ccorr->regs, DISP_CCORR_COEF_3); in mtk_ccorr_ctm_set()
112 &ccorr->cmdq_reg, ccorr->regs, DISP_CCORR_COEF_4); in mtk_ccorr_ctm_set()
152 ret = cmdq_dev_get_client_reg(dev, &priv->cmdq_reg, 0); in mtk_disp_ccorr_probe()
H A Dmtk_disp_ovl.c164 struct cmdq_client_reg cmdq_reg; member
292 &ovl->cmdq_reg, ovl->regs, in mtk_ovl_set_afbc()
309 &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_CLRFMT_EXT, in mtk_ovl_set_bit_depth()
320 mtk_ddp_write_relaxed(cmdq_pkt, h << 16 | w, &ovl->cmdq_reg, ovl->regs, in mtk_ovl_config()
327 mtk_ddp_write_relaxed(cmdq_pkt, OVL_COLOR_ALPHA, &ovl->cmdq_reg, in mtk_ovl_config()
330 mtk_ddp_write(cmdq_pkt, 0x1, &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_RST); in mtk_ovl_config()
331 mtk_ddp_write(cmdq_pkt, 0x0, &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_RST); in mtk_ovl_config()
376 mtk_ddp_write(cmdq_pkt, 0x1, &ovl->cmdq_reg, ovl->regs, in mtk_ovl_layer_on()
388 &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_RDMA_GMC(idx)); in mtk_ovl_layer_on()
389 mtk_ddp_write_mask(cmdq_pkt, BIT(idx), &ovl->cmdq_reg, ovl->regs, in mtk_ovl_layer_on()
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H A Dmtk_disp_aal.c49 struct cmdq_client_reg cmdq_reg; member
77 mtk_ddp_write(cmdq_pkt, sz, &aal->cmdq_reg, aal->regs, DISP_AAL_SIZE); in mtk_aal_config()
78 mtk_ddp_write(cmdq_pkt, sz, &aal->cmdq_reg, aal->regs, DISP_AAL_OUTPUT_SIZE); in mtk_aal_config()
188 ret = cmdq_dev_get_client_reg(dev, &priv->cmdq_reg, 0); in mtk_disp_aal_probe()
H A Dmtk_padding.c38 struct cmdq_client_reg cmdq_reg; member
116 ret = cmdq_dev_get_client_reg(dev, &priv->cmdq_reg, 0); in mtk_padding_probe()
H A Dmtk_ddp_comp.h357 struct cmdq_client_reg *cmdq_reg, void __iomem *regs,
360 struct cmdq_client_reg *cmdq_reg, void __iomem *regs,
363 struct cmdq_client_reg *cmdq_reg, void __iomem *regs,
H A Dmtk_disp_drv.h42 void mtk_dither_set_common(void __iomem *regs, struct cmdq_client_reg *cmdq_reg,
/linux/drivers/soc/mediatek/
H A Dmtk-mutex.c368 struct cmdq_client_reg cmdq_reg; member
996 if (!mtx->cmdq_reg.size) { in mtk_mutex_enable_by_cmdq()
1001 cmdq_pkt_write(cmdq_pkt, mtx->cmdq_reg.subsys, in mtk_mutex_enable_by_cmdq()
1123 ret = cmdq_dev_get_client_reg(dev, &mtx->cmdq_reg, 0); in mtk_mutex_probe()