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Searched refs:cmdq_base (Results 1 – 9 of 9) sorted by relevance

/linux/drivers/infiniband/hw/bnxt_re/
H A Dqplib_tlv.h48 static inline u8 __get_cmdq_base_opcode(struct cmdq_base *req, u32 size) in __get_cmdq_base_opcode()
51 return ((struct cmdq_base *)GET_TLV_DATA(req))->opcode; in __get_cmdq_base_opcode()
56 static inline void __set_cmdq_base_opcode(struct cmdq_base *req, in __set_cmdq_base_opcode()
60 ((struct cmdq_base *)GET_TLV_DATA(req))->opcode = val; in __set_cmdq_base_opcode()
65 static inline __le16 __get_cmdq_base_cookie(struct cmdq_base *req, u32 size) in __get_cmdq_base_cookie()
68 return ((struct cmdq_base *)GET_TLV_DATA(req))->cookie; in __get_cmdq_base_cookie()
73 static inline void __set_cmdq_base_cookie(struct cmdq_base *req, in __set_cmdq_base_cookie()
77 ((struct cmdq_base *)GET_TLV_DATA(req))->cookie = val; in __set_cmdq_base_cookie()
82 static inline __le64 __get_cmdq_base_resp_addr(struct cmdq_base *req, u32 size) in __get_cmdq_base_resp_addr()
85 return ((struct cmdq_base *)GET_TLV_DATA(req))->resp_addr; in __get_cmdq_base_resp_addr()
[all …]
H A Dqplib_rcfw.c459 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req, in __destroy_timedout_ah()
463 msg.req = (struct cmdq_base *)&req; in __destroy_timedout_ah()
818 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req, in bnxt_qplib_deinit_rcfw()
841 bnxt_qplib_rcfw_cmd_prep((struct cmdq_base *)&req, in bnxt_qplib_init_rcfw()
/linux/drivers/gpu/drm/mediatek/
H A Dmtk_ethdr.c73 struct cmdq_client_reg cmdq_base; member
178 mtk_ddp_write(cmdq_pkt, 0, &mixer->cmdq_base, mixer->regs, MIX_L_SRC_SIZE(idx)); in mtk_ethdr_layer_config()
206 mtk_ddp_write(cmdq_pkt, pending->height << 16 | align_width, &mixer->cmdq_base, in mtk_ethdr_layer_config()
208 mtk_ddp_write(cmdq_pkt, offset, &mixer->cmdq_base, mixer->regs, MIX_L_SRC_OFFSET(idx)); in mtk_ethdr_layer_config()
209 mtk_ddp_write(cmdq_pkt, alpha_con, &mixer->cmdq_base, mixer->regs, MIX_L_SRC_CON(idx)); in mtk_ethdr_layer_config()
210 mtk_ddp_write_mask(cmdq_pkt, BIT(idx), &mixer->cmdq_base, mixer->regs, MIX_SRC_CON, in mtk_ethdr_layer_config()
228 mtk_ddp_write(cmdq_pkt, HDR_VDO_FE_0804_BYPASS_ALL, &vdo_fe0->cmdq_base, in mtk_ethdr_config()
231 mtk_ddp_write(cmdq_pkt, HDR_VDO_FE_0804_BYPASS_ALL, &vdo_fe1->cmdq_base, in mtk_ethdr_config()
234 mtk_ddp_write(cmdq_pkt, HDR_GFX_FE_0204_BYPASS_ALL, &gfx_fe0->cmdq_base, in mtk_ethdr_config()
237 mtk_ddp_write(cmdq_pkt, HDR_GFX_FE_0204_BYPASS_ALL, &gfx_fe1->cmdq_base, in mtk_ethdr_config()
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/linux/tools/testing/selftests/kvm/lib/arm64/
H A Dgic_v3_its.c174 static void its_send_cmd(void *cmdq_base, struct its_cmd_block *cmd)
177 struct its_cmd_block *dst = cmdq_base + cwriter; in its_send_cmd()
206 void its_send_mapd_cmd(void *cmdq_base, u32 device_id, gpa_t itt_base,
217 its_send_cmd(cmdq_base, &cmd); in its_send_mapd_cmd()
220 void its_send_mapc_cmd(void *cmdq_base, u32 vcpu_id, u32 collection_id, bool valid)
229 its_send_cmd(cmdq_base, &cmd); in its_send_mapc_cmd()
232 void its_send_mapti_cmd(void *cmdq_base, u32 device_id, u32 event_id,
243 its_send_cmd(cmdq_base, &cmd); in its_send_mapti_cmd()
246 void its_send_invall_cmd(void *cmdq_base, u32 collection_id)
253 its_send_cmd(cmdq_base, in its_send_invall_cmd()
175 its_send_cmd(void * cmdq_base,struct its_cmd_block * cmd) its_send_cmd() argument
207 its_send_mapd_cmd(void * cmdq_base,u32 device_id,vm_paddr_t itt_base,size_t itt_size,bool valid) its_send_mapd_cmd() argument
221 its_send_mapc_cmd(void * cmdq_base,u32 vcpu_id,u32 collection_id,bool valid) its_send_mapc_cmd() argument
233 its_send_mapti_cmd(void * cmdq_base,u32 device_id,u32 event_id,u32 collection_id,u32 intid) its_send_mapti_cmd() argument
247 its_send_invall_cmd(void * cmdq_base,u32 collection_id) its_send_invall_cmd() argument
257 its_send_sync_cmd(void * cmdq_base,u32 vcpu_id) its_send_sync_cmd() argument
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/linux/tools/testing/selftests/kvm/include/arm64/
H A Dgic_v3_its.h11 void its_send_mapd_cmd(void *cmdq_base, u32 device_id, gpa_t itt_base,
13 void its_send_mapc_cmd(void *cmdq_base, u32 vcpu_id, u32 collection_id, bool valid);
14 void its_send_mapti_cmd(void *cmdq_base, u32 device_id, u32 event_id,
16 void its_send_invall_cmd(void *cmdq_base, u32 collection_id);
17 void its_send_sync_cmd(void *cmdq_base, u32 vcpu_id);
/linux/tools/testing/selftests/kvm/arm64/
H A Dvgic_lpi_stress.c40 gpa_t cmdq_base; member
117 test_data.cmdq_base, SZ_64K); in guest_setup_gic()
191 gpa_t cmdq_base; in setup_test_data() local
201 cmdq_base = vm_phy_pages_alloc(vm, pages_per_64k, gpa_base, in setup_test_data()
203 virt_map(vm, cmdq_base, cmdq_base, pages_per_64k); in setup_test_data()
204 test_data.cmdq_base = cmdq_base; in setup_test_data()
205 test_data.cmdq_base_va = (void *)cmdq_base; in setup_test_data()
/linux/drivers/infiniband/hw/bng_re/
H A Dbng_fw.h132 struct cmdq_base *req;
140 static inline void bng_re_rcfw_cmd_prep(struct cmdq_base *req, in bng_re_rcfw_cmd_prep()
163 static inline u32 bng_re_get_cmd_slots(struct cmdq_base *req) in bng_re_get_cmd_slots()
179 static inline u32 bng_re_set_cmd_slots(struct cmdq_base *req) in bng_re_set_cmd_slots()
H A Dbng_sp.c27 bng_re_rcfw_cmd_prep((struct cmdq_base *)&req, in bng_re_query_version()
53 bng_re_rcfw_cmd_prep((struct cmdq_base *)&req, in bng_re_get_dev_attr()
H A Dbng_fw.c711 bng_re_rcfw_cmd_prep((struct cmdq_base *)&req, in bng_re_deinit_rcfw()
746 bng_re_rcfw_cmd_prep((struct cmdq_base *)&req, in bng_re_init_rcfw()