Home
last modified time | relevance | path

Searched refs:cmdq (Results 1 – 25 of 56) sorted by relevance

123

/linux/drivers/gpu/drm/nouveau/nvkm/falcon/
H A Dcmdq.c26 nvkm_falcon_cmdq_has_room(struct nvkm_falcon_cmdq *cmdq, u32 size, bool *rewind) in nvkm_falcon_cmdq_has_room() argument
28 u32 head = nvkm_falcon_rd32(cmdq->qmgr->falcon, cmdq->head_reg); in nvkm_falcon_cmdq_has_room()
29 u32 tail = nvkm_falcon_rd32(cmdq->qmgr->falcon, cmdq->tail_reg); in nvkm_falcon_cmdq_has_room()
35 free = cmdq->offset + cmdq->size - head; in nvkm_falcon_cmdq_has_room()
40 head = cmdq->offset; in nvkm_falcon_cmdq_has_room()
51 nvkm_falcon_cmdq_push(struct nvkm_falcon_cmdq *cmdq, void *data, u32 size) in nvkm_falcon_cmdq_push() argument
53 struct nvkm_falcon *falcon = cmdq->qmgr->falcon; in nvkm_falcon_cmdq_push()
54 nvkm_falcon_pio_wr(falcon, data, 0, 0, DMEM, cmdq->position, size, 0, false); in nvkm_falcon_cmdq_push()
55 cmdq->position += ALIGN(size, QUEUE_ALIGNMENT); in nvkm_falcon_cmdq_push()
59 nvkm_falcon_cmdq_rewind(struct nvkm_falcon_cmdq *cmdq) in nvkm_falcon_cmdq_rewind() argument
[all …]
H A DKbuild3 nvkm-y += nvkm/falcon/cmdq.o
/linux/drivers/mailbox/
H A Dmtk-cmdq-mailbox.c77 struct cmdq *cmdq; member
84 struct cmdq { struct
119 struct cmdq *cmdq = container_of(chan->mbox, struct cmdq, mbox); in cmdq_get_mbox_priv() local
121 priv->shift_pa = cmdq->pdata->shift; in cmdq_get_mbox_priv()
122 priv->mminfra_offset = cmdq->pdata->mminfra_offset; in cmdq_get_mbox_priv()
128 struct cmdq *cmdq = container_of(chan->mbox, struct cmdq, mbox); in cmdq_get_shift_pa() local
130 return cmdq->pdata->shift; in cmdq_get_shift_pa()
134 static void cmdq_vm_init(struct cmdq *cmdq) in cmdq_vm_init() argument
140 if (!cmdq->pdata->gce_vm) in cmdq_vm_init()
143 vm_map = kcalloc(cmdq->pdata->thread_nr, sizeof(*vm_map), GFP_KERNEL); in cmdq_vm_init()
[all …]
/linux/drivers/crypto/cavium/nitrox/
H A Dnitrox_lib.c25 static int nitrox_cmdq_init(struct nitrox_cmdq *cmdq, int align_bytes) in nitrox_cmdq_init() argument
27 struct nitrox_device *ndev = cmdq->ndev; in nitrox_cmdq_init()
29 cmdq->qsize = (ndev->qlen * cmdq->instr_size) + align_bytes; in nitrox_cmdq_init()
30 cmdq->unalign_base = dma_alloc_coherent(DEV(ndev), cmdq->qsize, in nitrox_cmdq_init()
31 &cmdq->unalign_dma, in nitrox_cmdq_init()
33 if (!cmdq->unalign_base) in nitrox_cmdq_init()
36 cmdq->dma = PTR_ALIGN(cmdq->unalign_dma, align_bytes); in nitrox_cmdq_init()
37 cmdq->base = cmdq->unalign_base + (cmdq->dma - cmdq->unalign_dma); in nitrox_cmdq_init()
38 cmdq->write_idx = 0; in nitrox_cmdq_init()
40 spin_lock_init(&cmdq->cmd_qlock); in nitrox_cmdq_init()
[all …]
H A Dnitrox_reqmgr.c230 struct nitrox_cmdq *cmdq) in backlog_list_add() argument
234 spin_lock_bh(&cmdq->backlog_qlock); in backlog_list_add()
235 list_add_tail(&sr->backlog, &cmdq->backlog_head); in backlog_list_add()
236 atomic_inc(&cmdq->backlog_count); in backlog_list_add()
238 spin_unlock_bh(&cmdq->backlog_qlock); in backlog_list_add()
242 struct nitrox_cmdq *cmdq) in response_list_add() argument
246 spin_lock_bh(&cmdq->resp_qlock); in response_list_add()
247 list_add_tail(&sr->response, &cmdq->response_head); in response_list_add()
248 spin_unlock_bh(&cmdq->resp_qlock); in response_list_add()
252 struct nitrox_cmdq *cmdq) in response_list_del() argument
[all …]
H A Dnitrox_isr.c32 struct nitrox_cmdq *cmdq = qvec->cmdq; in nps_pkt_slc_isr() local
34 slc_cnts.value = readq(cmdq->compl_cnt_csr_addr); in nps_pkt_slc_isr()
337 qvec->cmdq = &ndev->pkt_inq[qvec->ring]; in nitrox_register_interrupts()
/linux/drivers/net/ethernet/brocade/bna/
H A Dbfa_msgq.c31 static void bfa_msgq_cmdq_dbell(struct bfa_msgq_cmdq *cmdq);
32 static void bfa_msgq_cmdq_copy_rsp(struct bfa_msgq_cmdq *cmdq);
43 bfa_fsm_state_decl(cmdq, stopped, struct bfa_msgq_cmdq, enum cmdq_event);
44 bfa_fsm_state_decl(cmdq, init_wait, struct bfa_msgq_cmdq, enum cmdq_event);
45 bfa_fsm_state_decl(cmdq, ready, struct bfa_msgq_cmdq, enum cmdq_event);
46 bfa_fsm_state_decl(cmdq, dbell_wait, struct bfa_msgq_cmdq,
50 cmdq_sm_stopped_entry(struct bfa_msgq_cmdq *cmdq) in cmdq_sm_stopped_entry() argument
54 cmdq->producer_index = 0; in cmdq_sm_stopped_entry()
55 cmdq->consumer_index = 0; in cmdq_sm_stopped_entry()
56 cmdq->flags = 0; in cmdq_sm_stopped_entry()
[all …]
/linux/drivers/accel/ivpu/
H A Divpu_job.c29 static void ivpu_cmdq_ring_db(struct ivpu_device *vdev, struct ivpu_cmdq *cmdq) in ivpu_cmdq_ring_db() argument
31 ivpu_hw_db_set(vdev, cmdq->db_id); in ivpu_cmdq_ring_db()
35 struct ivpu_file_priv *file_priv, struct ivpu_cmdq *cmdq) in ivpu_preemption_buffers_create() argument
40 cmdq->primary_preempt_buf = ivpu_bo_create(vdev, &file_priv->ctx, &vdev->hw->ranges.user, in ivpu_preemption_buffers_create()
43 if (!cmdq->primary_preempt_buf) { in ivpu_preemption_buffers_create()
48 cmdq->secondary_preempt_buf = ivpu_bo_create(vdev, &file_priv->ctx, &vdev->hw->ranges.dma, in ivpu_preemption_buffers_create()
51 if (!cmdq->secondary_preempt_buf) { in ivpu_preemption_buffers_create()
59 ivpu_bo_free(cmdq->primary_preempt_buf); in ivpu_preemption_buffers_create()
60 cmdq->primary_preempt_buf = NULL; in ivpu_preemption_buffers_create()
65 struct ivpu_file_priv *file_priv, struct ivpu_cmdq *cmdq) in ivpu_preemption_buffers_free() argument
[all …]
H A Divpu_mmu.c373 struct ivpu_mmu_queue *q = &mmu->cmdq; in ivpu_mmu_cmdq_alloc()
465 struct ivpu_mmu_queue *cmdq = &vdev->mmu->cmdq; in ivpu_mmu_cmdq_wait_for_cons() local
468 ret = REGV_POLL_FLD(IVPU_MMU_REG_CMDQ_CONS, VAL, cmdq->prod, in ivpu_mmu_cmdq_wait_for_cons()
473 cmdq->cons = cmdq->prod; in ivpu_mmu_cmdq_wait_for_cons()
492 struct ivpu_mmu_queue *cmdq = &vdev->mmu->cmdq; in ivpu_mmu_cmdq_cmd_write() local
493 u64 *queue_buffer = cmdq->base; in ivpu_mmu_cmdq_cmd_write()
494 int idx = IVPU_MMU_Q_IDX(cmdq->prod) * (IVPU_MMU_CMDQ_CMD_SIZE / sizeof(*queue_buffer)); in ivpu_mmu_cmdq_cmd_write()
496 if (ivpu_mmu_queue_is_full(cmdq)) { in ivpu_mmu_cmdq_cmd_write()
503 cmdq->prod = (cmdq->prod + 1) & IVPU_MMU_Q_WRAP_MASK; in ivpu_mmu_cmdq_cmd_write()
512 struct ivpu_mmu_queue *q = &vdev->mmu->cmdq; in ivpu_mmu_cmdq_sync()
[all …]
/linux/drivers/net/ethernet/huawei/hinic/
H A Dhinic_hw_cmdq.c78 #define cmdq_to_cmdqs(cmdq) container_of((cmdq) - (cmdq)->cmdq_type, \ argument
79 struct hinic_cmdqs, cmdq[0])
320 static void cmdq_set_db(struct hinic_cmdq *cmdq, in cmdq_set_db() argument
332 writel(db_info, CMDQ_DB_ADDR(cmdq->db_base, prod_idx)); in cmdq_set_db()
335 static int cmdq_sync_cmd_direct_resp(struct hinic_cmdq *cmdq, in cmdq_sync_cmd_direct_resp() argument
343 struct hinic_wq *wq = cmdq->wq; in cmdq_sync_cmd_direct_resp()
348 spin_lock_bh(&cmdq->cmdq_lock); in cmdq_sync_cmd_direct_resp()
353 spin_unlock_bh(&cmdq->cmdq_lock); in cmdq_sync_cmd_direct_resp()
359 wrapped = cmdq->wrapped; in cmdq_sync_cmd_direct_resp()
364 cmdq->wrapped = !cmdq->wrapped; in cmdq_sync_cmd_direct_resp()
[all …]
H A Dhinic_hw_io.c533 enum hinic_cmdq_type cmdq, type; in hinic_io_init() local
565 for (cmdq = HINIC_CMDQ_SYNC; cmdq < HINIC_MAX_CMDQ_TYPES; cmdq++) { in hinic_io_init()
573 func_to_io->cmdq_db_area[cmdq] = db_area; in hinic_io_init()
600 for (type = HINIC_CMDQ_SYNC; type < cmdq; type++) in hinic_io_init()
619 enum hinic_cmdq_type cmdq; in hinic_io_free() local
628 for (cmdq = HINIC_CMDQ_SYNC; cmdq < HINIC_MAX_CMDQ_TYPES; cmdq++) in hinic_io_free()
629 return_db_area(func_to_io, func_to_io->cmdq_db_area[cmdq]); in hinic_io_free()
/linux/drivers/infiniband/hw/bnxt_re/
H A Dqplib_rcfw.c114 struct bnxt_qplib_cmdq_ctx *cmdq; in bnxt_re_is_fw_stalled() local
118 cmdq = &rcfw->cmdq; in bnxt_re_is_fw_stalled()
120 if (time_after(jiffies, cmdq->last_seen + in bnxt_re_is_fw_stalled()
125 jiffies_to_msecs(jiffies - cmdq->last_seen), in bnxt_re_is_fw_stalled()
147 struct bnxt_qplib_cmdq_ctx *cmdq; in __wait_for_resp() local
151 cmdq = &rcfw->cmdq; in __wait_for_resp()
155 if (test_bit(ERR_DEVICE_DETACHED, &cmdq->flags)) in __wait_for_resp()
157 if (test_bit(FIRMWARE_STALL_DETECTED, &cmdq->flags)) in __wait_for_resp()
160 wait_event_timeout(cmdq->waitq, in __wait_for_resp()
162 test_bit(ERR_DEVICE_DETACHED, &cmdq->flags), in __wait_for_resp()
[all …]
/linux/drivers/net/ethernet/hisilicon/hns3/hns3_common/
H A Dhclge_comm_cmd.c541 struct hclge_comm_cmq *cmdq = &hw->cmq; in hclge_comm_cmd_uninit() local
550 spin_lock_bh(&cmdq->csq.lock); in hclge_comm_cmd_uninit()
551 spin_lock(&cmdq->crq.lock); in hclge_comm_cmd_uninit()
553 spin_unlock(&cmdq->crq.lock); in hclge_comm_cmd_uninit()
554 spin_unlock_bh(&cmdq->csq.lock); in hclge_comm_cmd_uninit()
556 hclge_comm_free_cmd_desc(&cmdq->csq); in hclge_comm_cmd_uninit()
557 hclge_comm_free_cmd_desc(&cmdq->crq); in hclge_comm_cmd_uninit()
563 struct hclge_comm_cmq *cmdq = &hw->cmq; in hclge_comm_cmd_queue_init() local
567 spin_lock_init(&cmdq->csq.lock); in hclge_comm_cmd_queue_init()
568 spin_lock_init(&cmdq->crq.lock); in hclge_comm_cmd_queue_init()
[all …]
/linux/drivers/gpu/drm/nouveau/nvkm/engine/sec2/
H A Dbase.c45 struct nvkm_falcon_cmdq *cmdq = sec2->cmdq; in nvkm_sec2_fini() local
56 ret = nvkm_falcon_cmdq_send(cmdq, &cmd, nvkm_sec2_finimsg, sec2, in nvkm_sec2_fini()
68 nvkm_falcon_cmdq_fini(cmdq); in nvkm_sec2_fini()
119 nvkm_falcon_cmdq_del(&sec2->cmdq); in nvkm_sec2_dtor()
159 (ret = nvkm_falcon_cmdq_new(sec2->qmgr, "cmdq", &sec2->cmdq)) || in nvkm_sec2_new_()
H A Dga102.c50 nvkm_falcon_cmdq_init(sec2->cmdq, msg.queue_info[i].index, in ga102_sec2_initmsg()
104 return nvkm_falcon_cmdq_send(sec2->cmdq, &cmd.cmd.hdr, in ga102_sec2_acr_bootstrap_falcon()
137 .cmdq = { 0xc00, 0xc04, 8 },
H A Dgp102.c71 return nvkm_falcon_cmdq_send(sec2->cmdq, &cmd.cmd.hdr, in gp102_sec2_acr_bootstrap_falcon()
142 nvkm_falcon_cmdq_init(sec2->cmdq, in gp102_sec2_initmsg()
214 .cmdq = { 0xa00, 0xa04, 8 },
/linux/drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/
H A Drpc.c369 msg->sequence = gsp->cmdq.seq++; in r535_gsp_cmdq_push()
377 wptr = *gsp->cmdq.wptr; in r535_gsp_cmdq_push()
380 free = *gsp->cmdq.rptr + gsp->cmdq.cnt - wptr - 1; in r535_gsp_cmdq_push()
381 if (free >= gsp->cmdq.cnt) in r535_gsp_cmdq_push()
382 free -= gsp->cmdq.cnt; in r535_gsp_cmdq_push()
394 cqe = (void *)((u8 *)gsp->shm.cmdq.ptr + 0x1000 + wptr * 0x1000); in r535_gsp_cmdq_push()
395 step = min_t(u32, free, (gsp->cmdq.cnt - wptr)); in r535_gsp_cmdq_push()
401 if (wptr == gsp->cmdq.cnt) in r535_gsp_cmdq_push()
410 (*gsp->cmdq.wptr) = wptr; in r535_gsp_cmdq_push()
541 mutex_lock(&gsp->cmdq.mutex); in r535_gsp_rpc_poll()
[all …]
H A Dgsp.c53 mutex_lock(&gsp->cmdq.mutex); in r535_gsp_msgq_work()
56 mutex_unlock(&gsp->cmdq.mutex); in r535_gsp_msgq_work()
1140 } *cmdq, *msgq; in r535_gsp_shared_init() local
1143 gsp->shm.cmdq.size = 0x40000; in r535_gsp_shared_init()
1146 gsp->shm.ptes.nr = (gsp->shm.cmdq.size + gsp->shm.msgq.size) >> GSP_PAGE_SHIFT; in r535_gsp_shared_init()
1151 gsp->shm.cmdq.size + in r535_gsp_shared_init()
1158 gsp->shm.cmdq.ptr = (u8 *)gsp->shm.ptes.ptr + gsp->shm.ptes.size; in r535_gsp_shared_init()
1159 gsp->shm.msgq.ptr = (u8 *)gsp->shm.cmdq.ptr + gsp->shm.cmdq.size; in r535_gsp_shared_init()
1164 cmdq = gsp->shm.cmdq.ptr; in r535_gsp_shared_init()
1165 cmdq->tx.version = 0; in r535_gsp_shared_init()
[all …]
/linux/drivers/iommu/arm/arm-smmu-v3/
H A Darm-smmu-v3.h709 static inline bool arm_smmu_cmdq_supports_cmd(struct arm_smmu_cmdq *cmdq, in arm_smmu_cmdq_supports_cmd() argument
712 return cmdq->supports_cmd ? cmdq->supports_cmd(cmd) : true; in arm_smmu_cmdq_supports_cmd()
717 struct arm_smmu_cmdq *cmdq; member
939 struct arm_smmu_cmdq cmdq; member
1167 struct arm_smmu_cmdq *cmdq);
1173 struct arm_smmu_cmdq *cmdq);
1217 struct arm_smmu_cmdq *cmdq,
1221 struct arm_smmu_cmdq *cmdq,
/linux/drivers/infiniband/hw/hns/
H A Dhns_roce_trace.h175 DECLARE_EVENT_CLASS(cmdq,
201 DEFINE_EVENT(cmdq, hns_cmdq_req,
205 DEFINE_EVENT(cmdq, hns_cmdq_resp,
/linux/drivers/media/platform/mediatek/mdp3/
H A DMakefile4 mtk-mdp3-y += mtk-mdp3-comp.o mtk-mdp3-cmdq.o
/linux/drivers/iommu/riscv/
H A Diommu.c514 riscv_iommu_queue_send(&iommu->cmdq, cmd, sizeof(*cmd), NULL); in riscv_iommu_cmd_send()
526 ret = riscv_iommu_queue_send(&iommu->cmdq, &cmd, sizeof(cmd), &prod); in riscv_iommu_cmd_sync()
533 if (riscv_iommu_queue_wait(&iommu->cmdq, prod, timeout_us)) in riscv_iommu_cmd_sync()
1576 riscv_iommu_queue_disable(&iommu->cmdq); in riscv_iommu_remove()
1584 RISCV_IOMMU_QUEUE_INIT(&iommu->cmdq, CQ); in riscv_iommu_init()
1585 raw_spin_lock_init(&iommu->cmdq.lock); in riscv_iommu_init()
1596 rc = riscv_iommu_queue_alloc(iommu, &iommu->cmdq, in riscv_iommu_init()
1606 rc = riscv_iommu_queue_enable(iommu, &iommu->cmdq, riscv_iommu_cmdq_process); in riscv_iommu_init()
1647 riscv_iommu_queue_disable(&iommu->cmdq); in riscv_iommu_init()
/linux/drivers/gpu/drm/nouveau/include/nvkm/engine/
H A Dsec2.h17 struct nvkm_falcon_cmdq *cmdq; member
/linux/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/
H A Dgp102.c40 .cmdq = { 0x4a0, 0x4b0, 4 },
/linux/tools/testing/selftests/kvm/include/arm64/
H A Dgic_v3_its.h9 size_t device_tbl_sz, gpa_t cmdq, size_t cmdq_size);

123