Home
last modified time | relevance | path

Searched refs:clr_mask (Results 1 – 12 of 12) sorted by relevance

/linux/drivers/hwmon/
H A Dlm75.c86 u16 clr_mask; member
132 .clr_mask = 1 << 5, /* not one-shot mode */
154 .clr_mask = 3 << 5,
163 .clr_mask = 3 << 5,
172 .clr_mask = 3 << 5,
236 .clr_mask = 1 << 7, /* not one-shot mode */
246 .clr_mask = 1 << 7, /* not one-shot mode */
255 .clr_mask = 1 << 7, /* not one-shot mode */
264 .clr_mask = 1 << 7, /* not one-shot mode*/
274 .clr_mask = 1 << 15, /* no one-shot mode*/
[all …]
H A Dmax31730.c61 u8 clr_mask) in max31730_write_config() argument
65 clr_mask |= MAX31730_EXTRANGE; in max31730_write_config()
66 value = data->current_conf & ~clr_mask; in max31730_write_config()
/linux/drivers/net/ethernet/microchip/
H A Dencx24j600-regmap.c196 unsigned int clr_mask = mask & ~val; in regmap_encx24j600_reg_update_bits() local
209 if ((clr_mask & 0xff) && (ret == 0)) in regmap_encx24j600_reg_update_bits()
210 ret = regmap_encx24j600_sfr_clr_bits(ctx, reg, clr_mask); in regmap_encx24j600_reg_update_bits()
212 clr_mask = (clr_mask & 0xff00) >> 8; in regmap_encx24j600_reg_update_bits()
214 if ((clr_mask & 0xff) && (ret == 0)) in regmap_encx24j600_reg_update_bits()
215 ret = regmap_encx24j600_sfr_clr_bits(ctx, reg + 1, clr_mask); in regmap_encx24j600_reg_update_bits()
/linux/drivers/infiniband/hw/mthca/
H A Dmthca_eq.c397 if (dev->eq_table.clr_mask) in mthca_tavor_interrupt()
398 writel(dev->eq_table.clr_mask, dev->eq_table.clr_int); in mthca_tavor_interrupt()
437 if (dev->eq_table.clr_mask) in mthca_arbel_interrupt()
438 writel(dev->eq_table.clr_mask, dev->eq_table.clr_int); in mthca_arbel_interrupt()
786 dev->eq_table.clr_mask = 0; in mthca_init_eq_table()
788 dev->eq_table.clr_mask = in mthca_init_eq_table()
H A Dmthca_dev.h228 u32 clr_mask; member
/linux/drivers/net/phy/
H A Dbcm7xxx.c224 int set_mask, int clr_mask) in __phy_set_clr_bits() argument
232 v &= ~clr_mask; in __phy_set_clr_bits()
243 int set_mask, int clr_mask) in phy_set_clr_bits() argument
248 ret = __phy_set_clr_bits(dev, location, set_mask, clr_mask); in phy_set_clr_bits()
/linux/drivers/mfd/
H A Dssbi.c93 static int ssbi_wait_mask(struct ssbi *ssbi, u32 set_mask, u32 clr_mask) in ssbi_wait_mask() argument
100 if (((val & set_mask) == set_mask) && ((val & clr_mask) == 0)) in ssbi_wait_mask()
/linux/drivers/gpio/
H A Dgpio-rtd.c428 u32 clr_mask = BIT(hwirq % 31) << 1; in rtd_gpio_enable_irq() local
444 writel_relaxed(clr_mask, data->irq_base + gpa_reg_offset); in rtd_gpio_enable_irq()
445 writel_relaxed(clr_mask, data->irq_base + gpda_reg_offset); in rtd_gpio_enable_irq()
/linux/drivers/media/i2c/
H A Dths8200.c98 uint8_t clr_mask, uint8_t val_mask) in ths8200_write_and_or() argument
100 ths8200_write(sd, reg, (ths8200_read(sd, reg) & clr_mask) | val_mask); in ths8200_write_and_or()
H A Dadv7511-v4l2.c209 static inline void adv7511_wr_and_or(struct v4l2_subdev *sd, u8 reg, u8 clr_mask, u8 val_mask) in adv7511_wr_and_or() argument
211 adv7511_wr(sd, reg, (adv7511_rd(sd, reg) & clr_mask) | val_mask); in adv7511_wr_and_or()
/linux/drivers/net/ethernet/mellanox/mlx4/
H A Deq.c856 writel(priv->eq_table.clr_mask, priv->eq_table.clr_int); in mlx4_interrupt()
1205 priv->eq_table.clr_mask = in mlx4_init_eq_table()
H A Dmlx4.h695 u32 clr_mask; member