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Searched refs:clr_mask (Results 1 – 10 of 10) sorted by relevance

/linux/drivers/hwmon/
H A Dlm75.c89 u16 clr_mask; member
136 .clr_mask = 1 << 5, /* not one-shot mode */
158 .clr_mask = 3 << 5,
167 .clr_mask = 3 << 5,
176 .clr_mask = 3 << 5,
230 .clr_mask = 1 << 1 | 1 << 7, /* disable SMBAlert and one-shot */
237 .clr_mask = 1 << 1 | 1 << 7, /* disable SMBAlert and one-shot */
254 .clr_mask = 1 << 7, /* not one-shot mode */
264 .clr_mask = 1 << 7, /* not one-shot mode */
273 .clr_mask = 1 << 7, /* not one-shot mode */
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/linux/drivers/net/ethernet/microchip/
H A Dencx24j600-regmap.c196 unsigned int clr_mask = mask & ~val; in regmap_encx24j600_reg_update_bits() local
209 if ((clr_mask & 0xff) && (ret == 0)) in regmap_encx24j600_reg_update_bits()
210 ret = regmap_encx24j600_sfr_clr_bits(ctx, reg, clr_mask); in regmap_encx24j600_reg_update_bits()
212 clr_mask = (clr_mask & 0xff00) >> 8; in regmap_encx24j600_reg_update_bits()
214 if ((clr_mask & 0xff) && (ret == 0)) in regmap_encx24j600_reg_update_bits()
215 ret = regmap_encx24j600_sfr_clr_bits(ctx, reg + 1, clr_mask); in regmap_encx24j600_reg_update_bits()
/linux/drivers/infiniband/hw/mthca/
H A Dmthca_eq.c397 if (dev->eq_table.clr_mask) in mthca_tavor_interrupt()
398 writel(dev->eq_table.clr_mask, dev->eq_table.clr_int); in mthca_tavor_interrupt()
437 if (dev->eq_table.clr_mask) in mthca_arbel_interrupt()
438 writel(dev->eq_table.clr_mask, dev->eq_table.clr_int); in mthca_arbel_interrupt()
785 dev->eq_table.clr_mask = 0; in mthca_init_eq_table()
787 dev->eq_table.clr_mask = in mthca_init_eq_table()
H A Dmthca_dev.h228 u32 clr_mask; member
/linux/drivers/net/phy/
H A Dbcm7xxx.c224 int set_mask, int clr_mask) in __phy_set_clr_bits() argument
232 v &= ~clr_mask; in __phy_set_clr_bits()
243 int set_mask, int clr_mask) in phy_set_clr_bits() argument
248 ret = __phy_set_clr_bits(dev, location, set_mask, clr_mask); in phy_set_clr_bits()
/linux/drivers/mfd/
H A Dssbi.c93 static int ssbi_wait_mask(struct ssbi *ssbi, u32 set_mask, u32 clr_mask) in ssbi_wait_mask() argument
100 if (((val & set_mask) == set_mask) && ((val & clr_mask) == 0)) in ssbi_wait_mask()
/linux/drivers/gpio/
H A Dgpio-rtd.c430 u32 clr_mask = BIT(hwirq % 31) << 1; in rtd_gpio_enable_irq() local
446 writel_relaxed(clr_mask, data->irq_base + gpa_reg_offset); in rtd_gpio_enable_irq()
447 writel_relaxed(clr_mask, data->irq_base + gpda_reg_offset); in rtd_gpio_enable_irq()
/linux/drivers/dma/qcom/
H A Dbam_dma.c920 u32 clr_mask = 0, srcs = 0; in bam_dma_irq() local
934 clr_mask = readl_relaxed(bam_addr(bdev, 0, BAM_IRQ_STTS)); in bam_dma_irq()
942 writel_relaxed(clr_mask, bam_addr(bdev, 0, BAM_IRQ_CLR)); in bam_dma_irq()
/linux/drivers/net/ethernet/mellanox/mlx4/
H A Deq.c856 writel(priv->eq_table.clr_mask, priv->eq_table.clr_int); in mlx4_interrupt()
1203 priv->eq_table.clr_mask = in mlx4_init_eq_table()
H A Dmlx4.h695 u32 clr_mask; member