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Searched refs:clr_bits (Results 1 – 7 of 7) sorted by relevance

/linux/drivers/gpu/drm/xe/
H A Dxe_rtp.h244 .clr_bits = ~0u, .set_bits = (val_), \
262 .clr_bits = val_, .set_bits = val_, \
280 .clr_bits = val_, .set_bits = 0, \
297 .clr_bits = mask_bits_, .set_bits = val_, \
302 .clr_bits = (mask_bits_), .set_bits = (val_), \
318 .clr_bits = RING_FORCE_TO_NONPRIV_MASK_VALID, \
H A Dxe_reg_sr_types.h16 u32 clr_bits; member
H A Dxe_gt.c201 if (entry->reg.masked || entry->clr_bits == ~0) in emit_wa_job()
241 val = entry->clr_bits << 16; in emit_wa_job()
242 else if (entry->clr_bits == ~0) in emit_wa_job()
259 if (entry->reg.masked || entry->clr_bits == ~0) in emit_wa_job()
269 *cs++ = entry->clr_bits; in emit_wa_job()
288 entry->reg.addr, entry->clr_bits, entry->set_bits); in emit_wa_job()
H A Dxe_rtp_types.h29 u32 clr_bits; member
H A Dxe_rtp.c177 .clr_bits = action->clr_bits, in rtp_add_sr_entry()
/linux/drivers/gpu/drm/sprd/
H A Dsprd_dpu.h83 dpu_reg_clr(struct dpu_context *ctx, u32 offset, u32 clr_bits) in dpu_reg_clr() argument
87 writel(bits & ~clr_bits, ctx->base + offset); in dpu_reg_clr()
/linux/drivers/gpu/drm/i915/display/
H A Dintel_ddi.c3060 u32 clr_bits, wait_bits; in mtl_ddi_disable_d2d() local
3067 clr_bits = XE2LPD_DDI_BUF_D2D_LINK_ENABLE; in mtl_ddi_disable_d2d()
3071 clr_bits = XELPDP_PORT_BUF_D2D_LINK_ENABLE; in mtl_ddi_disable_d2d()
3075 intel_de_rmw(display, reg, clr_bits, 0); in mtl_ddi_disable_d2d()