Searched refs:clock_limits (Results 1 – 7 of 7) sorted by relevance
98 .clock_limits = {267 struct _vcs_dpi_voltage_scaling_st *clock_limits = in dcn351_update_bw_bounding_box_fpu() local268 dc->scratch.update_bw_bounding_box.clock_limits; in dcn351_update_bw_bounding_box_fpu()292 if (dcn3_51_soc.clock_limits[j].dcfclk_mhz <= in dcn351_update_bw_bounding_box_fpu()303 clock_limits[i].state = i; in dcn351_update_bw_bounding_box_fpu()306 clock_limits[i].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz; in dcn351_update_bw_bounding_box_fpu()308 clock_limits[i].dcfclk_mhz < in dcn351_update_bw_bounding_box_fpu()309 dcn3_51_soc.clock_limits[closest_clk_lvl].dcfclk_mhz) { in dcn351_update_bw_bounding_box_fpu()311 clock_limits[i].dcfclk_mhz = in dcn351_update_bw_bounding_box_fpu()312 dcn3_51_soc.clock_limits[closest_clk_lvl].dcfclk_mhz; in dcn351_update_bw_bounding_box_fpu()[all …]
119 .clock_limits = {233 struct _vcs_dpi_voltage_scaling_st *clock_limits = in dcn35_update_bw_bounding_box_fpu() local234 dc->scratch.update_bw_bounding_box.clock_limits; in dcn35_update_bw_bounding_box_fpu()258 if (dcn3_5_soc.clock_limits[j].dcfclk_mhz <= in dcn35_update_bw_bounding_box_fpu()269 clock_limits[i].state = i; in dcn35_update_bw_bounding_box_fpu()272 clock_limits[i].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz; in dcn35_update_bw_bounding_box_fpu()274 clock_limits[i].dcfclk_mhz < in dcn35_update_bw_bounding_box_fpu()275 dcn3_5_soc.clock_limits[closest_clk_lvl].dcfclk_mhz) { in dcn35_update_bw_bounding_box_fpu()277 clock_limits[i].dcfclk_mhz = in dcn35_update_bw_bounding_box_fpu()278 dcn3_5_soc.clock_limits[closest_clk_lvl].dcfclk_mhz; in dcn35_update_bw_bounding_box_fpu()[all …]
122 .clock_limits = {366 .clock_limits = {508 pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].socclk_mhz; in dcn31_calculate_wm_and_dlg_fp()548 pipes[pipe_idx].clks_cfg.dispclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dispclk_mhz; in dcn31_calculate_wm_and_dlg_fp()549 pipes[pipe_idx].clks_cfg.dppclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dppclk_mhz; in dcn31_calculate_wm_and_dlg_fp()592 struct _vcs_dpi_voltage_scaling_st *s = dc->scratch.update_bw_bounding_box.clock_limits; in dcn31_update_bw_bounding_box()600 memcpy(s, dcn3_1_soc.clock_limits, sizeof(dcn3_1_soc.clock_limits)); in dcn31_update_bw_bounding_box()620 if ((unsigned int) dcn3_1_soc.clock_limits[j].dcfclk_mhz <= clk_table->entries[i].dcfclk_mhz) { in dcn31_update_bw_bounding_box()637 dcn3_1_soc.clock_limits[closest_clk_lvl].dispclk_mhz; in dcn31_update_bw_bounding_box()640 dcn3_1_soc.clock_limits[closest_clk_lvl].dppclk_mhz; in dcn31_update_bw_bounding_box()[all …]
377 if (soc->clock_limits[i].state == mode_lib->vba.VoltageLevel) in fetch_socbb_params()380 mode_lib->vba.DCFCLK = soc->clock_limits[i].dcfclk_mhz; in fetch_socbb_params()381 mode_lib->vba.SOCCLK = soc->clock_limits[i].socclk_mhz; in fetch_socbb_params()382 mode_lib->vba.DRAMSpeed = soc->clock_limits[i].dram_speed_mts; in fetch_socbb_params()383 mode_lib->vba.FabricClock = soc->clock_limits[i].fabricclk_mhz; in fetch_socbb_params()395 mode_lib->vba.DCFCLKPerState[i] = soc->clock_limits[i].dcfclk_mhz; in fetch_socbb_params()396 mode_lib->vba.FabricClockPerState[i] = soc->clock_limits[i].fabricclk_mhz; in fetch_socbb_params()397 mode_lib->vba.SOCCLKPerState[i] = soc->clock_limits[i].socclk_mhz; in fetch_socbb_params()398 mode_lib->vba.PHYCLKPerState[i] = soc->clock_limits[i].phyclk_mhz; in fetch_socbb_params()399 mode_lib->vba.PHYCLKD18PerState[i] = soc->clock_limits[i].phyclk_d18_mhz; in fetch_socbb_params()[all …]
182 struct _vcs_dpi_voltage_scaling_st clock_limits[DC__VOLTAGE_STATES]; member
79 struct gpu_info_voltage_scaling_v1_0 clock_limits[8]; member
1792 struct _vcs_dpi_voltage_scaling_st clock_limits[DC__VOLTAGE_STATES]; member