Searched refs:clock_limits (Results 1 – 9 of 9) sorted by relevance
122 .clock_limits = {366 .clock_limits = {508 pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].socclk_mhz; in dcn31_calculate_wm_and_dlg_fp()548 pipes[pipe_idx].clks_cfg.dispclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dispclk_mhz; in dcn31_calculate_wm_and_dlg_fp()549 pipes[pipe_idx].clks_cfg.dppclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dppclk_mhz; in dcn31_calculate_wm_and_dlg_fp()592 struct _vcs_dpi_voltage_scaling_st *s = dc->scratch.update_bw_bounding_box.clock_limits; in dcn31_update_bw_bounding_box_fpu()600 memcpy(s, dcn3_1_soc.clock_limits, sizeof(dcn3_1_soc.clock_limits)); in dcn31_update_bw_bounding_box_fpu()620 if ((unsigned int) dcn3_1_soc.clock_limits[j].dcfclk_mhz <= clk_table->entries[i].dcfclk_mhz) { in dcn31_update_bw_bounding_box_fpu()637 dcn3_1_soc.clock_limits[closest_clk_lvl].dispclk_mhz; in dcn31_update_bw_bounding_box_fpu()640 dcn3_1_soc.clock_limits[closest_clk_lvl].dppclk_mhz; in dcn31_update_bw_bounding_box_fpu()[all …]
222 .clock_limits = {333 .clock_limits = {444 .clock_limits = {625 .clock_limits = {1218 …context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz = context->bw_ctx.dml.soc.clock_limits[vlevel]… in dcn20_calculate_dlg_params()1219 …context->bw_ctx.bw.dcn.clk.max_supported_dispclk_khz = context->bw_ctx.dml.soc.clock_limits[vlevel… in dcn20_calculate_dlg_params()1769 pipes[pipe_cnt].clks_cfg.dispclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dispclk_mhz; in dcn20_calculate_wm()1770 pipes[pipe_cnt].clks_cfg.dppclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dppclk_mhz; in dcn20_calculate_wm()1792 pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].dcfclk_mhz; in dcn20_calculate_wm()1793 pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].socclk_mhz; in dcn20_calculate_wm()[all …]
127 .clock_limits = {197 …uint16_t dcfclk_mhz_for_the_second_state = clk_mgr->base.ctx->dc->dml.soc.clock_limits[2].dcfclk_m… in dcn32_build_wm_range_table_fpu()1743 …context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz = context->bw_ctx.dml.soc.clock_limits[vlevel]… in dcn32_calculate_dlg_params()1745 …context->bw_ctx.bw.dcn.clk.max_supported_dispclk_khz = context->bw_ctx.dml.soc.clock_limits[vlevel… in dcn32_calculate_dlg_params()2271 double dcfclk = dcn3_2_soc.clock_limits[0].dcfclk_mhz; in dcn32_calculate_wm_and_dlg_fpu()2394 dcfclk = dcn3_2_soc.clock_limits[2].dcfclk_mhz; in dcn32_calculate_wm_and_dlg_fpu()2400 pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel_temp].socclk_mhz; in dcn32_calculate_wm_and_dlg_fpu()2465 pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].socclk_mhz; in dcn32_calculate_wm_and_dlg_fpu()2566 pipes[pipe_idx].clks_cfg.dispclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dispclk_mhz; in dcn32_calculate_wm_and_dlg_fpu()2567 pipes[pipe_idx].clks_cfg.dppclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dppclk_mhz; in dcn32_calculate_wm_and_dlg_fpu()[all …]
377 if (soc->clock_limits[i].state == mode_lib->vba.VoltageLevel) in fetch_socbb_params()380 mode_lib->vba.DCFCLK = soc->clock_limits[i].dcfclk_mhz; in fetch_socbb_params()381 mode_lib->vba.SOCCLK = soc->clock_limits[i].socclk_mhz; in fetch_socbb_params()382 mode_lib->vba.DRAMSpeed = soc->clock_limits[i].dram_speed_mts; in fetch_socbb_params()383 mode_lib->vba.FabricClock = soc->clock_limits[i].fabricclk_mhz; in fetch_socbb_params()395 mode_lib->vba.DCFCLKPerState[i] = soc->clock_limits[i].dcfclk_mhz; in fetch_socbb_params()396 mode_lib->vba.FabricClockPerState[i] = soc->clock_limits[i].fabricclk_mhz; in fetch_socbb_params()397 mode_lib->vba.SOCCLKPerState[i] = soc->clock_limits[i].socclk_mhz; in fetch_socbb_params()398 mode_lib->vba.PHYCLKPerState[i] = soc->clock_limits[i].phyclk_mhz; in fetch_socbb_params()399 mode_lib->vba.PHYCLKD18PerState[i] = soc->clock_limits[i].phyclk_d18_mhz; in fetch_socbb_params()[all …]
182 struct _vcs_dpi_voltage_scaling_st clock_limits[DC__VOLTAGE_STATES]; member
79 struct gpu_info_voltage_scaling_v1_0 clock_limits[8]; member
725 out->state_array[i].dcfclk_mhz = dc->dml.soc.clock_limits[i].dcfclk_mhz; in dml2_translate_soc_states()726 out->state_array[i].dispclk_mhz = dc->dml.soc.clock_limits[i].dispclk_mhz; in dml2_translate_soc_states()727 out->state_array[i].dppclk_mhz = dc->dml.soc.clock_limits[i].dppclk_mhz; in dml2_translate_soc_states()728 out->state_array[i].dram_speed_mts = dc->dml.soc.clock_limits[i].dram_speed_mts; in dml2_translate_soc_states()729 out->state_array[i].dtbclk_mhz = dc->dml.soc.clock_limits[i].dtbclk_mhz; in dml2_translate_soc_states()730 out->state_array[i].socclk_mhz = dc->dml.soc.clock_limits[i].socclk_mhz; in dml2_translate_soc_states()731 out->state_array[i].fabricclk_mhz = dc->dml.soc.clock_limits[i].fabricclk_mhz; in dml2_translate_soc_states()732 out->state_array[i].dscclk_mhz = dc->dml.soc.clock_limits[i].dscclk_mhz; in dml2_translate_soc_states()733 out->state_array[i].phyclk_d18_mhz = dc->dml.soc.clock_limits[i].phyclk_d18_mhz; in dml2_translate_soc_states()734 out->state_array[i].phyclk_d32_mhz = dc->dml.soc.clock_limits[i].phyclk_d32_mhz; in dml2_translate_soc_states()[all …]
140 .clock_limits = {
1863 struct _vcs_dpi_voltage_scaling_st clock_limits[DC__VOLTAGE_STATES]; member