Home
last modified time | relevance | path

Searched refs:clock_cfg (Results 1 – 7 of 7) sorted by relevance

/linux/drivers/net/ethernet/marvell/octeontx2/af/
H A Dptp.c372 u64 clock_cfg; in ptp_start() local
398 clock_cfg = readq(ptp->reg_base + PTP_CLOCK_CFG); in ptp_start()
403 clock_cfg &= ~PTP_CLOCK_CFG_EXT_CLK_IN_MASK; in ptp_start()
404 clock_cfg |= PTP_CLOCK_CFG_EXT_CLK_EN; in ptp_start()
408 clock_cfg |= PTP_CLOCK_CFG_TSTMP_EDGE; in ptp_start()
410 clock_cfg &= ~PTP_CLOCK_CFG_TSTMP_IN_MASK; in ptp_start()
411 clock_cfg |= PTP_CLOCK_CFG_TSTMP_EN; in ptp_start()
414 clock_cfg |= PTP_CLOCK_CFG_PTP_EN; in ptp_start()
415 writeq(clock_cfg, ptp->reg_base + PTP_CLOCK_CFG); in ptp_start()
416 clock_cfg = readq(ptp->reg_base + PTP_CLOCK_CFG); in ptp_start()
[all …]
/linux/drivers/net/ethernet/cavium/common/
H A Dcavium_ptp.c226 u64 clock_cfg; in cavium_ptp_probe() local
274 clock_cfg = readq(clock->reg_base + PTP_CLOCK_CFG); in cavium_ptp_probe()
275 clock_cfg |= PTP_CLOCK_CFG_PTP_EN; in cavium_ptp_probe()
276 writeq(clock_cfg, clock->reg_base + PTP_CLOCK_CFG); in cavium_ptp_probe()
291 clock_cfg = readq(clock->reg_base + PTP_CLOCK_CFG); in cavium_ptp_probe()
292 clock_cfg &= ~PTP_CLOCK_CFG_PTP_EN; in cavium_ptp_probe()
293 writeq(clock_cfg, clock->reg_base + PTP_CLOCK_CFG); in cavium_ptp_probe()
313 u64 clock_cfg; in cavium_ptp_remove() local
320 clock_cfg = readq(clock->reg_base + PTP_CLOCK_CFG); in cavium_ptp_remove()
321 clock_cfg &= ~PTP_CLOCK_CFG_PTP_EN; in cavium_ptp_remove()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/
H A Ddcn20_clk_mgr.c455 struct dc_clock_config *clock_cfg) in dcn2_get_clock()
459 clock_cfg->max_clock_khz = context->bw_ctx.bw.dcn.clk.max_supported_dispclk_khz; in dcn2_get_clock()
460 clock_cfg->min_clock_khz = DCN_MINIMUM_DISPCLK_Khz; in dcn2_get_clock()
461 clock_cfg->current_clock_khz = clk_mgr->clks.dispclk_khz; in dcn2_get_clock()
462 clock_cfg->bw_requirequired_clock_khz = context->bw_ctx.bw.dcn.clk.bw_dispclk_khz; in dcn2_get_clock()
465 clock_cfg->max_clock_khz = context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz; in dcn2_get_clock()
466 clock_cfg->min_clock_khz = DCN_MINIMUM_DPPCLK_Khz; in dcn2_get_clock()
467 clock_cfg->current_clock_khz = clk_mgr->clks.dppclk_khz; in dcn2_get_clock()
468 clock_cfg->bw_requirequired_clock_khz = context->bw_ctx.bw.dcn.clk.bw_dppclk_khz;
452 dcn2_get_clock(struct clk_mgr * clk_mgr,struct dc_state * context,enum dc_clock_type clock_type,struct dc_clock_config * clock_cfg) dcn2_get_clock() argument
H A Ddcn20_clk_mgr.h51 struct dc_clock_config *clock_cfg);
/linux/drivers/clk/stm32/
H A Dclk-stm32-core.h50 void *clock_cfg; member
167 .clock_cfg = (_struct) {_clk},\
/linux/drivers/gpu/drm/amd/display/dc/
H A Ddc.h2908 void dc_get_clock(struct dc *dc, enum dc_clock_type clock_type, struct dc_clock_config *clock_cfg);
/linux/drivers/gpu/drm/amd/display/dc/core/
H A Ddc.c6245 void dc_get_clock(struct dc *dc, enum dc_clock_type clock_type, struct dc_clock_config *clock_cfg)
6248 dc->hwss.get_clock(dc, clock_type, clock_cfg);
5689 dc_get_clock(struct dc * dc,enum dc_clock_type clock_type,struct dc_clock_config * clock_cfg) dc_get_clock() argument