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Searched refs:clks (Results 1 – 25 of 597) sorted by relevance

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/linux/drivers/clk/imx/
H A Dclk-imx8ulp.c149 struct clk_hw **clks; in imx8ulp_clk_cgc1_init() local
158 clks = clk_data->hws; in imx8ulp_clk_cgc1_init()
160 clks[IMX8ULP_CLK_DUMMY] = imx_clk_hw_fixed("dummy", 0); in imx8ulp_clk_cgc1_init()
167 …clks[IMX8ULP_CLK_SPLL2_PRE_SEL] = imx_clk_hw_mux_flags("spll2_pre_sel", base + 0x510, 0, 1, pll_pr… in imx8ulp_clk_cgc1_init()
168 …clks[IMX8ULP_CLK_SPLL3_PRE_SEL] = imx_clk_hw_mux_flags("spll3_pre_sel", base + 0x610, 0, 1, pll_pr… in imx8ulp_clk_cgc1_init()
170 …clks[IMX8ULP_CLK_SPLL2] = imx_clk_hw_pllv4(IMX_PLLV4_IMX8ULP_1GHZ, "spll2", "spll2_pre_sel", base … in imx8ulp_clk_cgc1_init()
171 …clks[IMX8ULP_CLK_SPLL3] = imx_clk_hw_pllv4(IMX_PLLV4_IMX8ULP, "spll3", "spll3_pre_sel", base + 0x6… in imx8ulp_clk_cgc1_init()
172 clks[IMX8ULP_CLK_SPLL3_VCODIV] = imx_clk_hw_divider("spll3_vcodiv", "spll3", base + 0x604, 0, 6); in imx8ulp_clk_cgc1_init()
174 …clks[IMX8ULP_CLK_SPLL3_PFD0] = imx_clk_hw_pfdv2(IMX_PFDV2_IMX8ULP, "spll3_pfd0", "spll3_vcodiv", b… in imx8ulp_clk_cgc1_init()
175 …clks[IMX8ULP_CLK_SPLL3_PFD1] = imx_clk_hw_pfdv2(IMX_PFDV2_IMX8ULP, "spll3_pfd1", "spll3_vcodiv", b… in imx8ulp_clk_cgc1_init()
[all …]
/linux/drivers/clk/hisilicon/
H A Dclk.c51 clk_data->clk_data.clks = clk_table; in hisi_clk_alloc()
80 clk_data->clk_data.clks = clk_table; in hisi_clk_init()
91 int hisi_clk_register_fixed_rate(const struct hisi_fixed_rate_clock *clks, in hisi_clk_register_fixed_rate() argument
98 clk = clk_register_fixed_rate(NULL, clks[i].name, in hisi_clk_register_fixed_rate()
99 clks[i].parent_name, in hisi_clk_register_fixed_rate()
100 clks[i].flags, in hisi_clk_register_fixed_rate()
101 clks[i].fixed_rate); in hisi_clk_register_fixed_rate()
104 __func__, clks[i].name); in hisi_clk_register_fixed_rate()
107 data->clk_data.clks[clks[i].id] = clk; in hisi_clk_register_fixed_rate()
114 clk_unregister_fixed_rate(data->clk_data.clks[clks[i].id]); in hisi_clk_register_fixed_rate()
[all …]
/linux/drivers/clk/mmp/
H A Dclk.c21 unit->clk_data.clks = clk_table; in mmp_clk_init()
27 struct mmp_param_fixed_rate_clk *clks, in mmp_register_fixed_rate_clks() argument
34 clk = clk_register_fixed_rate(NULL, clks[i].name, in mmp_register_fixed_rate_clks()
35 clks[i].parent_name, in mmp_register_fixed_rate_clks()
36 clks[i].flags, in mmp_register_fixed_rate_clks()
37 clks[i].fixed_rate); in mmp_register_fixed_rate_clks()
40 __func__, clks[i].name); in mmp_register_fixed_rate_clks()
43 if (clks[i].id) in mmp_register_fixed_rate_clks()
44 unit->clk_table[clks[i].id] = clk; in mmp_register_fixed_rate_clks()
49 struct mmp_param_fixed_factor_clk *clks, in mmp_register_fixed_factor_clks() argument
[all …]
/linux/drivers/clk/mxs/
H A Dclk-imx28.c145 static struct clk *clks[clk_max]; variable
167 clks[ref_xtal] = mxs_clk_fixed("ref_xtal", 24000000); in mx28_clocks_init()
168 clks[pll0] = mxs_clk_pll("pll0", "ref_xtal", PLL0CTRL0, 17, 480000000); in mx28_clocks_init()
169 clks[pll1] = mxs_clk_pll("pll1", "ref_xtal", PLL1CTRL0, 17, 480000000); in mx28_clocks_init()
170 clks[pll2] = mxs_clk_pll("pll2", "ref_xtal", PLL2CTRL0, 23, 50000000); in mx28_clocks_init()
171 clks[ref_cpu] = mxs_clk_ref("ref_cpu", "pll0", FRAC0, 0); in mx28_clocks_init()
172 clks[ref_emi] = mxs_clk_ref("ref_emi", "pll0", FRAC0, 1); in mx28_clocks_init()
173 clks[ref_io1] = mxs_clk_ref("ref_io1", "pll0", FRAC0, 2); in mx28_clocks_init()
174 clks[ref_io0] = mxs_clk_ref("ref_io0", "pll0", FRAC0, 3); in mx28_clocks_init()
175 clks[ref_pix] = mxs_clk_ref("ref_pix", "pll0", FRAC1, 0); in mx28_clocks_init()
[all …]
H A Dclk-imx23.c90 static struct clk *clks[clk_max]; variable
112 clks[ref_xtal] = mxs_clk_fixed("ref_xtal", 24000000); in mx23_clocks_init()
113 clks[pll] = mxs_clk_pll("pll", "ref_xtal", PLLCTRL0, 16, 480000000); in mx23_clocks_init()
114 clks[ref_cpu] = mxs_clk_ref("ref_cpu", "pll", FRAC, 0); in mx23_clocks_init()
115 clks[ref_emi] = mxs_clk_ref("ref_emi", "pll", FRAC, 1); in mx23_clocks_init()
116 clks[ref_pix] = mxs_clk_ref("ref_pix", "pll", FRAC, 2); in mx23_clocks_init()
117 clks[ref_io] = mxs_clk_ref("ref_io", "pll", FRAC, 3); in mx23_clocks_init()
118 clks[saif_sel] = mxs_clk_mux("saif_sel", CLKSEQ, 0, 1, sel_pll, ARRAY_SIZE(sel_pll)); in mx23_clocks_init()
119 clks[lcdif_sel] = mxs_clk_mux("lcdif_sel", CLKSEQ, 1, 1, sel_pix, ARRAY_SIZE(sel_pix)); in mx23_clocks_init()
120 clks[gpmi_sel] = mxs_clk_mux("gpmi_sel", CLKSEQ, 4, 1, sel_io, ARRAY_SIZE(sel_io)); in mx23_clocks_init()
[all …]
/linux/drivers/clk/
H A Dclk-bulk.c16 struct clk_bulk_data *clks) in of_clk_bulk_get() argument
22 clks[i].id = NULL; in of_clk_bulk_get()
23 clks[i].clk = NULL; in of_clk_bulk_get()
27 of_property_read_string_index(np, "clock-names", i, &clks[i].id); in of_clk_bulk_get()
28 clks[i].clk = of_clk_get(np, i); in of_clk_bulk_get()
29 if (IS_ERR(clks[i].clk)) { in of_clk_bulk_get()
30 ret = PTR_ERR(clks[i].clk); in of_clk_bulk_get()
33 clks[i].clk = NULL; in of_clk_bulk_get()
41 clk_bulk_put(i, clks); in of_clk_bulk_get()
47 struct clk_bulk_data **clks) in of_clk_bulk_get_all() argument
[all …]
/linux/drivers/clk/socfpga/
H A Dclk-gate-s10.c127 struct clk_hw *s10_register_gate(const struct stratix10_gate_clock *clks, void __iomem *regbase) in s10_register_gate() argument
132 const char *parent_name = clks->parent_name; in s10_register_gate()
139 socfpga_clk->hw.reg = regbase + clks->gate_reg; in s10_register_gate()
140 socfpga_clk->hw.bit_idx = clks->gate_idx; in s10_register_gate()
145 socfpga_clk->fixed_div = clks->fixed_div; in s10_register_gate()
147 if (clks->div_reg) in s10_register_gate()
148 socfpga_clk->div_reg = regbase + clks->div_reg; in s10_register_gate()
152 socfpga_clk->width = clks->div_width; in s10_register_gate()
153 socfpga_clk->shift = clks->div_offset; in s10_register_gate()
155 if (clks->bypass_reg) in s10_register_gate()
[all …]
H A Dclk-periph-s10.c101 struct clk_hw *s10_register_periph(const struct stratix10_perip_c_clock *clks, in s10_register_periph() argument
107 const char *name = clks->name; in s10_register_periph()
108 const char *parent_name = clks->parent_name; in s10_register_periph()
115 periph_clk->hw.reg = reg + clks->offset; in s10_register_periph()
119 init.flags = clks->flags; in s10_register_periph()
121 init.num_parents = clks->num_parents; in s10_register_periph()
124 init.parent_data = clks->parent_data; in s10_register_periph()
137 struct clk_hw *n5x_register_periph(const struct n5x_perip_c_clock *clks, in n5x_register_periph() argument
143 const char *name = clks->name; in n5x_register_periph()
144 const char *parent_name = clks->parent_name; in n5x_register_periph()
[all …]
/linux/arch/powerpc/platforms/512x/
H A Dclock-commonclk.c70 static struct clk *clks[MPC512x_CLK_LAST_PRIVATE]; variable
403 for (i = 0; i < ARRAY_SIZE(clks); i++) in mpc512x_clk_preset_data()
404 clks[i] = ERR_PTR(-ENODEV); in mpc512x_clk_preset_data()
446 clks[MPC512x_CLK_REF] = mpc512x_clk_factor("ref", "osc", 1, 1); in mpc512x_clk_setup_ref_clock()
447 calc_freq = clk_get_rate(clks[MPC512x_CLK_REF]); in mpc512x_clk_setup_ref_clock()
461 clks[MPC512x_CLK_REF] = mpc512x_clk_fixed("ref", calc_freq); in mpc512x_clk_setup_ref_clock()
650 div = clk_get_rate(clks[MPC512x_CLK_SYS]); in mpc512x_clk_setup_mclk()
651 div /= clk_get_rate(clks[MPC512x_CLK_IPS]); in mpc512x_clk_setup_mclk()
674 clks[clks_idx_int + MCLK_IDX_MUX0] = mpc512x_clk_muxed( in mpc512x_clk_setup_mclk()
681 clks[clks_idx_int + MCLK_IDX_EN0] = mpc512x_clk_gated( in mpc512x_clk_setup_mclk()
[all …]
/linux/drivers/clk/axis/
H A Dclk-artpec6.c43 struct clk **clks; in of_artpec6_clkctrl_setup() local
56 clks = clkdata->clk_table; in of_artpec6_clkctrl_setup()
59 clks[i] = ERR_PTR(-EPROBE_DEFER); in of_artpec6_clkctrl_setup()
85 clks[ARTPEC6_CLK_CPU] = in of_artpec6_clkctrl_setup()
88 clks[ARTPEC6_CLK_CPU_PERIPH] = in of_artpec6_clkctrl_setup()
92 clks[ARTPEC6_CLK_UART_PCLK] = in of_artpec6_clkctrl_setup()
94 clks[ARTPEC6_CLK_UART_REFCLK] = in of_artpec6_clkctrl_setup()
98 clks[ARTPEC6_CLK_SPI_PCLK] = in of_artpec6_clkctrl_setup()
100 clks[ARTPEC6_CLK_SPI_SSPCLK] = in of_artpec6_clkctrl_setup()
104 clks[ARTPEC6_CLK_DBG_PCLK] = in of_artpec6_clkctrl_setup()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/
H A Ddcn20_clk_mgr.c109 clk_mgr->dccg->ref_dppclk = clk_mgr->base.clks.dppclk_khz; in dcn20_update_clocks_update_dpp_dto()
136 if (clk_mgr->base.clks.dppclk_khz == 0 || clk_mgr->base.clks.dispclk_khz == 0) in dcn20_update_clocks_update_dentist()
140 * clk_mgr->base.dentist_vco_freq_khz / clk_mgr->base.clks.dppclk_khz; in dcn20_update_clocks_update_dentist()
142 * clk_mgr->base.dentist_vco_freq_khz / clk_mgr->base.clks.dispclk_khz; in dcn20_update_clocks_update_dentist()
237 if (clk_mgr_base->clks.dispclk_khz == 0 || in dcn2_update_clocks()
262 if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr_base->clks.dcfclk_khz)) { in dcn2_update_clocks()
263 clk_mgr_base->clks.dcfclk_khz = new_clocks->dcfclk_khz; in dcn2_update_clocks()
265 …pp_smu->set_hard_min_dcfclk_by_freq(&pp_smu->pp_smu, khz_to_mhz_ceil(clk_mgr_base->clks.dcfclk_khz… in dcn2_update_clocks()
269 new_clocks->dcfclk_deep_sleep_khz, clk_mgr_base->clks.dcfclk_deep_sleep_khz)) { in dcn2_update_clocks()
270 clk_mgr_base->clks.dcfclk_deep_sleep_khz = new_clocks->dcfclk_deep_sleep_khz; in dcn2_update_clocks()
[all …]
/linux/arch/powerpc/boot/dts/
H A Dmpc5121.dtsi50 clocks = <&clks MPC512x_CLK_MBX_BUS>,
51 <&clks MPC512x_CLK_MBX_3D>,
52 <&clks MPC512x_CLK_MBX>;
67 clocks = <&clks MPC512x_CLK_NFC>;
134 clks: clock@f00 { label
159 clocks = <&clks MPC512x_CLK_BDLC>,
160 <&clks MPC512x_CLK_IPS>,
161 <&clks MPC512x_CLK_SYS>,
162 <&clks MPC512x_CLK_REF>,
163 <&clks MPC512x_CLK_MSCAN0_MCLK>;
[all …]
/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx53.dtsi56 clocks = <&clks IMX5_CLK_ARM>;
121 clocks = <&clks IMX5_CLK_USB_PHY1_GATE>;
129 clocks = <&clks IMX5_CLK_USB_PHY2_GATE>;
146 clocks = <&clks IMX5_CLK_SATA_GATE>,
147 <&clks IMX5_CLK_SATA_REF>,
148 <&clks IMX5_CLK_AHB>;
159 clocks = <&clks IMX5_CLK_IPU_GATE>,
160 <&clks IMX5_CLK_IPU_DI0_GATE>,
161 <&clks IMX5_CLK_IPU_DI1_GATE>;
221 clocks = <&clks IMX5_CLK_GPU3D_GATE>, <&clks IMX5_CLK_GARB_GATE>;
[all …]
H A Dimx51.dtsi83 clocks = <&clks IMX5_CLK_CPU_PODF>;
102 clocks = <&clks IMX5_CLK_USB_PHY_GATE>;
138 clocks = <&clks IMX5_CLK_GPU3D_GATE>, <&clks IMX5_CLK_GARB_GATE>;
148 clocks = <&clks IMX5_CLK_IPU_GATE>,
149 <&clks IMX5_CLK_IPU_DI0_GATE>,
150 <&clks IMX5_CLK_IPU_DI1_GATE>;
195 clocks = <&clks IMX5_CLK_ESDHC1_IPG_GATE>,
196 <&clks IMX5_CLK_DUMMY>,
197 <&clks IMX5_CLK_ESDHC1_PER_GATE>;
206 clocks = <&clks IMX5_CLK_ESDHC2_IPG_GATE>,
[all …]
H A Dimx50.dtsi91 clocks = <&clks IMX5_CLK_USB_PHY1_GATE>;
122 clocks = <&clks IMX5_CLK_ESDHC1_IPG_GATE>,
123 <&clks IMX5_CLK_DUMMY>,
124 <&clks IMX5_CLK_ESDHC1_PER_GATE>;
134 clocks = <&clks IMX5_CLK_ESDHC2_IPG_GATE>,
135 <&clks IMX5_CLK_DUMMY>,
136 <&clks IMX5_CLK_ESDHC2_PER_GATE>;
146 clocks = <&clks IMX5_CLK_UART3_IPG_GATE>,
147 <&clks IMX5_CLK_UART3_PER_GATE>;
158 clocks = <&clks IMX5_CLK_ECSPI1_IPG_GATE>,
[all …]
H A Dimx6q.dtsi42 clocks = <&clks IMX6QDL_CLK_ARM>,
43 <&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
44 <&clks IMX6QDL_CLK_STEP>,
45 <&clks IMX6QDL_CLK_PLL1_SW>,
46 <&clks IMX6QDL_CLK_PLL1_SYS>;
79 clocks = <&clks IMX6QDL_CLK_ARM>,
80 <&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
81 <&clks IMX6QDL_CLK_STEP>,
82 <&clks IMX6QDL_CLK_PLL1_SW>,
83 <&clks IMX6QDL_CLK_PLL1_SYS>;
[all …]
H A Dimx6qp.dtsi15 clocks = <&clks IMX6QDL_CLK_OCRAM>;
24 clocks = <&clks IMX6QDL_CLK_OCRAM>;
32 clocks = <&clks IMX6QDL_CLK_PRE0>;
41 clocks = <&clks IMX6QDL_CLK_PRE1>;
50 clocks = <&clks IMX6QDL_CLK_PRE2>;
59 clocks = <&clks IMX6QDL_CLK_PRE3>;
67 clocks = <&clks IMX6QDL_CLK_PRG0_APB>,
68 <&clks IMX6QDL_CLK_PRG0_AXI>;
76 clocks = <&clks IMX6QDL_CLK_PRG1_APB>,
77 <&clks IMX6QDL_CLK_PRG1_AXI>;
[all …]
H A Dimxrt1050.dtsi35 clocks = <&clks IMXRT1050_CLK_LPUART1>;
51 clks: clock-controller@400fc000 { label
58 assigned-clocks = <&clks IMXRT1050_CLK_PLL1_BYPASS>,
59 <&clks IMXRT1050_CLK_PLL1_BYPASS>,
60 <&clks IMXRT1050_CLK_PLL2_BYPASS>,
61 <&clks IMXRT1050_CLK_PLL3_BYPASS>,
62 <&clks IMXRT1050_CLK_PLL3_PFD1_664_62M>,
63 <&clks IMXRT1050_CLK_PLL2_PFD2_396M>;
64 assigned-clock-parents = <&clks IMXRT1050_CLK_PLL1_REF_SEL>,
65 <&clks IMXRT1050_CLK_PLL1_ARM>,
[all …]
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn201/
H A Ddcn201_clk_mgr.c77 memset(&(clk_mgr->clks), 0, sizeof(struct dc_clocks)); in dcn201_init_clocks()
78 clk_mgr->clks.p_state_change_support = true; in dcn201_init_clocks()
79 clk_mgr->clks.prev_p_state_change_support = true; in dcn201_init_clocks()
80 clk_mgr->clks.max_supported_dppclk_khz = 1200000; in dcn201_init_clocks()
81 clk_mgr->clks.max_supported_dispclk_khz = 1200000; in dcn201_init_clocks()
101 if (clk_mgr_base->clks.dispclk_khz == 0 || in dcn201_update_clocks()
116 if (should_set_clock(safe_to_lower, new_clocks->phyclk_khz, clk_mgr_base->clks.phyclk_khz)) in dcn201_update_clocks()
117 clk_mgr_base->clks.phyclk_khz = new_clocks->phyclk_khz; in dcn201_update_clocks()
123 if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr_base->clks.dcfclk_khz)) in dcn201_update_clocks()
124 clk_mgr_base->clks.dcfclk_khz = new_clocks->dcfclk_khz; in dcn201_update_clocks()
[all …]
/linux/arch/arm64/boot/dts/freescale/
H A Ds32g2.dtsi99 clks: protocol@14 { label
121 clocks = <&clks 54>, <&clks 55>;
338 clocks = <&clks 0x3a>, <&clks 0x3b>, <&clks 0x3b>;
346 clocks = <&clks 0x3a>, <&clks 0x3b>, <&clks 0x3b>;
354 clocks = <&clks 0x3a>, <&clks 0x3b>, <&clks 0x3b>;
362 clocks = <&clks 0x3a>, <&clks 0x3b>, <&clks 0x3b>;
371 clocks = <&clks 0x3b>, <&clks 0x3c>, <&clks 0x3c>;
380 clocks = <&clks 0x3b>, <&clks 0x3c>, <&clks 0x3c>;
389 clocks = <&clks 0x3b>, <&clks 0x3c>, <&clks 0x3c>;
398 clocks = <&clks 0x3b>, <&clks 0x3c>, <&clks 0x3c>;
[all …]
/linux/drivers/clk/zynq/
H A Dclkc.c62 static struct clk *clks[clk_max]; variable
147 clks[fclk] = clk_register_gate(NULL, clk_name, in zynq_clk_register_fclk()
152 if (clk_prepare_enable(clks[fclk])) in zynq_clk_register_fclk()
171 clks[fclk] = ERR_PTR(-ENOMEM); in zynq_clk_register_fclk()
197 clks[clk0] = clk_register_gate(NULL, clk_name0, div_name, in zynq_clk_register_periph_clk()
200 clks[clk1] = clk_register_gate(NULL, clk_name1, div_name, in zynq_clk_register_periph_clk()
209 clks[clk0] = ERR_PTR(-ENOMEM); in zynq_clk_register_periph_clk()
211 clks[clk1] = ERR_PTR(-ENOMEM); in zynq_clk_register_periph_clk()
260 clks[armpll] = clk_register_mux(NULL, clk_output_name[armpll], in zynq_clk_setup()
266 clks[ddrpll] = clk_register_mux(NULL, clk_output_name[ddrpll], in zynq_clk_setup()
[all …]
/linux/drivers/clk/microchip/
H A Dclk-pic32mzda.c128 struct clk *clks[MAXCLKS]; member
157 struct clk **clks; in pic32mzda_clk_probe() local
173 clks = &cd->clks[0]; in pic32mzda_clk_probe()
176 clks[POSCCLK] = clk_register_fixed_rate(&pdev->dev, "posc_clk", NULL, in pic32mzda_clk_probe()
178 clks[FRCCLK] = clk_register_fixed_rate(&pdev->dev, "frc_clk", NULL, in pic32mzda_clk_probe()
180 clks[BFRCCLK] = clk_register_fixed_rate(&pdev->dev, "bfrc_clk", NULL, in pic32mzda_clk_probe()
182 clks[LPRCCLK] = clk_register_fixed_rate(&pdev->dev, "lprc_clk", NULL, in pic32mzda_clk_probe()
184 clks[UPLLCLK] = clk_register_fixed_rate(&pdev->dev, "usbphy_clk", NULL, in pic32mzda_clk_probe()
189 clks[SOSCCLK] = pic32_sosc_clk_register(&sosc_clk, core); in pic32mzda_clk_probe()
192 clks[FRCDIVCLK] = clk_register_divider(&pdev->dev, "frcdiv_clk", in pic32mzda_clk_probe()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/
H A Ddcn42_clk_mgr.c174 clk_mgr->dccg->ref_dppclk = clk_mgr->base.clks.dppclk_khz; in dcn42_update_clocks_update_dpp_dto()
237 new_clocks->zstate_support != clk_mgr_base->clks.zstate_support) { in dcn42_update_clocks()
239 clk_mgr_base->clks.zstate_support = new_clocks->zstate_support; in dcn42_update_clocks()
242 if (clk_mgr_base->clks.dtbclk_en && !new_clocks->dtbclk_en) { in dcn42_update_clocks()
245 clk_mgr_base->clks.dtbclk_en = new_clocks->dtbclk_en; in dcn42_update_clocks()
248 if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_LOW_POWER) { in dcn42_update_clocks()
251 clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_LOW_POWER; in dcn42_update_clocks()
255 new_clocks->zstate_support != clk_mgr_base->clks.zstate_support) { in dcn42_update_clocks()
257 clk_mgr_base->clks.zstate_support = new_clocks->zstate_support; in dcn42_update_clocks()
263 if (!clk_mgr_base->clks.dtbclk_en && new_clocks->dtbclk_en) { in dcn42_update_clocks()
[all …]
/linux/drivers/cpufreq/
H A Dimx6q-cpufreq.c42 static struct clk_bulk_data clks[] = { variable
70 old_freq = clk_get_rate(clks[ARM].clk) / 1000; in imx6q_set_target()
129 clk_set_rate(clks[ARM].clk, (old_freq >> 1) * 1000); in imx6q_set_target()
130 clk_set_parent(clks[PLL1_SW].clk, clks[PLL1_SYS].clk); in imx6q_set_target()
131 if (freq_hz > clk_get_rate(clks[PLL2_PFD2_396M].clk)) in imx6q_set_target()
132 clk_set_parent(clks[SECONDARY_SEL].clk, in imx6q_set_target()
133 clks[PLL2_BUS].clk); in imx6q_set_target()
135 clk_set_parent(clks[SECONDARY_SEL].clk, in imx6q_set_target()
136 clks[PLL2_PFD2_396M].clk); in imx6q_set_target()
137 clk_set_parent(clks[STEP].clk, clks[SECONDARY_SEL].clk); in imx6q_set_target()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/
H A Drv1_clk_mgr.c36 memset(&(clk_mgr->clks), 0, sizeof(struct dc_clocks)); in rv1_init_clocks()
42 bool dispclk_increase = new_clocks->dispclk_khz > clk_mgr->base.clks.dispclk_khz; in rv1_determine_dppclk_threshold()
44 bool cur_dpp_div = clk_mgr->base.clks.dispclk_khz > clk_mgr->base.clks.dppclk_khz; in rv1_determine_dppclk_threshold()
74 if (clk_mgr->base.clks.dispclk_khz <= disp_clk_threshold) in rv1_determine_dppclk_threshold()
182 clk_mgr->base.clks.dispclk_khz = new_clocks->dispclk_khz; in ramp_up_dispclk_with_dpp()
183 clk_mgr->base.clks.dppclk_khz = new_clocks->dppclk_khz; in ramp_up_dispclk_with_dpp()
184 clk_mgr->base.clks.max_supported_dppclk_khz = new_clocks->max_supported_dppclk_khz; in ramp_up_dispclk_with_dpp()
224 if (new_clocks->dispclk_khz > clk_mgr_base->clks.dispclk_khz in rv1_update_clocks()
225 || new_clocks->phyclk_khz > clk_mgr_base->clks.phyclk_khz in rv1_update_clocks()
226 || new_clocks->fclk_khz > clk_mgr_base->clks.fclk_khz in rv1_update_clocks()
[all …]

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