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Searched refs:clk_zero (Results 1 – 7 of 7) sorted by relevance

/linux/drivers/gpu/drm/msm/dsi/phy/
H A Ddsi_phy.c49 timing->clk_zero = clk_z + 8 - temp; in dsi_dphy_timing_calc_clk_zero()
120 temp += ((timing->clk_zero >> 1) + 1) * 2 * ui; in msm_dsi_dphy_timing_calc()
139 timing->shared_timings.clk_pre_inc_by_2, timing->clk_zero, in msm_dsi_dphy_timing_calc()
192 timing->clk_zero = linear_inter(tmax, tmin, pcnt5, 0, false); in msm_dsi_dphy_timing_calc_v2()
232 temp += (((timing->clk_zero + 3) << 3) + 11 - (pd_ckln << 1)) * ui; in msm_dsi_dphy_timing_calc_v2()
253 timing->shared_timings.clk_pre_inc_by_2, timing->clk_zero, in msm_dsi_dphy_timing_calc_v2()
300 timing->clk_zero = linear_inter(tmax, tmin, pcnt5, 0, false); in msm_dsi_dphy_timing_calc_v3()
340 temp += (((timing->clk_zero + 3) << 3) + 11) * ui; in msm_dsi_dphy_timing_calc_v3()
363 timing->shared_timings.clk_pre_inc_by_2, timing->clk_zero, in msm_dsi_dphy_timing_calc_v3()
413 timing->clk_zero = linear_inter(tmax, tmin, pcnt_clk_zero, 0, false); in msm_dsi_dphy_timing_calc_v4()
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H A Ddsi_phy_20nm.c15 writel(DSI_20nm_PHY_TIMING_CTRL_0_CLK_ZERO(timing->clk_zero), in dsi_20nm_dphy_set_timing()
21 if (timing->clk_zero & BIT(8)) in dsi_20nm_dphy_set_timing()
H A Ddsi_phy.h69 u32 clk_zero; member
H A Ddsi_phy_7nm.c1161 writel(timing->clk_zero, base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_1); in dsi_7nm_phy_enable()
/linux/drivers/phy/
H A Dphy-core-mipi-dphy.c46 cfg->clk_zero = 262000; in phy_mipi_dphy_calc_config()
138 if ((cfg->clk_prepare + cfg->clk_zero) < 300000) in phy_mipi_dphy_config_validate()
/linux/include/linux/phy/
H A Dphy-mipi-dphy.h100 unsigned int clk_zero; member
/linux/drivers/phy/amlogic/
H A Dphy-meson-axg-mipi-dphy.c251 (DIV_ROUND_UP(priv->config.clk_zero, temp) << 16) | in phy_meson_axg_mipi_dphy_power_on()