Searched refs:clk_zero (Results 1 – 6 of 6) sorted by relevance
46 cfg->clk_zero = 262000; in phy_mipi_dphy_calc_config()138 if ((cfg->clk_prepare + cfg->clk_zero) < 300000) in phy_mipi_dphy_config_validate()
15 writel(DSI_20nm_PHY_TIMING_CTRL_0_CLK_ZERO(timing->clk_zero), in dsi_20nm_dphy_set_timing()21 if (timing->clk_zero & BIT(8)) in dsi_20nm_dphy_set_timing()
1161 writel(timing->clk_zero, base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_1); in dsi_7nm_phy_enable()
100 unsigned int clk_zero; member
251 (DIV_ROUND_UP(priv->config.clk_zero, temp) << 16) | in phy_meson_axg_mipi_dphy_power_on()
929 int clk_prepare, lpx, clk_zero, clk_post, clk_trail; in samsung_dsim_set_phy_ctrl() local958 clk_zero = PS_TO_CYCLE(cfg.clk_zero, byte_clock); in samsung_dsim_set_phy_ctrl()996 DSIM_PHYTIMING1_CLK_ZERO(clk_zero) | in samsung_dsim_set_phy_ctrl()