Searched refs:clk_zero (Results 1 – 5 of 5) sorted by relevance
46 cfg->clk_zero = 262000; in phy_mipi_dphy_calc_config()138 if ((cfg->clk_prepare + cfg->clk_zero) < 300000) in phy_mipi_dphy_config_validate()
15 writel(DSI_20nm_PHY_TIMING_CTRL_0_CLK_ZERO(timing->clk_zero), in dsi_20nm_dphy_set_timing()21 if (timing->clk_zero & BIT(8)) in dsi_20nm_dphy_set_timing()
100 unsigned int clk_zero; member
250 (DIV_ROUND_UP(priv->config.clk_zero, temp) << 16) | in phy_meson_axg_mipi_dphy_power_on()
314 u8 clk_zero; member1245 val = T_CLK_ZERO(timing->clk_zero) | T_CLK_PREPARE(timing->clk_prepare); in samsung_mipi_dphy_clk_lane_timing_init()