Searched refs:clk_settle (Results 1 – 5 of 5) sorted by relevance
43 cfg->clk_settle = 95000; in phy_mipi_dphy_calc_config()129 if (cfg->clk_settle < 95000 || cfg->clk_settle > 300000) in phy_mipi_dphy_config_validate()
332 u32 clk_settle; member340 u32 clk_settle; member627 csis->clk_settle = 0; in mipi_csis_calculate_params()630 lane_rate, csis->clk_settle, csis->hs_settle); in mipi_csis_calculate_params()638 if (csis->debug.clk_settle < 4) { in mipi_csis_calculate_params()640 csis->debug.clk_settle); in mipi_csis_calculate_params()641 csis->clk_settle = csis->debug.clk_settle; in mipi_csis_calculate_params()665 MIPI_CSIS_DPHY_CMN_CTRL_CLKSETTLE(csis->clk_settle)); in mipi_csis_set_params()931 csis->debug.clk_settle = UINT_MAX; in mipi_csis_debugfs_init()940 &csis->debug.clk_settle); in mipi_csis_debugfs_init()
71 unsigned int clk_settle; member
325 s32 clk_settle; member
327 timing->clk_settle = cio2_rx_timing(CIO2_CSIRX_DLY_CNT_SETTLE_CLANE_A, in cio2_csi2_calc_timing()341 dev_dbg(dev, "freq cs value is %d\n", timing->clk_settle); in cio2_csi2_calc_timing()375 writel(timing.clk_settle, q->csi_rx_base + in cio2_hw_init()