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Searched refs:clk_set_parent (Results 1 – 25 of 61) sorted by relevance

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/linux/drivers/clk/imx/
H A Dclk-imx6sx.c177 clk_set_parent(hws[IMX6SX_PLL1_BYPASS]->clk, hws[IMX6SX_CLK_PLL1]->clk); in imx6sx_clocks_init()
178 clk_set_parent(hws[IMX6SX_PLL2_BYPASS]->clk, hws[IMX6SX_CLK_PLL2]->clk); in imx6sx_clocks_init()
179 clk_set_parent(hws[IMX6SX_PLL3_BYPASS]->clk, hws[IMX6SX_CLK_PLL3]->clk); in imx6sx_clocks_init()
180 clk_set_parent(hws[IMX6SX_PLL4_BYPASS]->clk, hws[IMX6SX_CLK_PLL4]->clk); in imx6sx_clocks_init()
181 clk_set_parent(hws[IMX6SX_PLL5_BYPASS]->clk, hws[IMX6SX_CLK_PLL5]->clk); in imx6sx_clocks_init()
182 clk_set_parent(hws[IMX6SX_PLL6_BYPASS]->clk, hws[IMX6SX_CLK_PLL6]->clk); in imx6sx_clocks_init()
183 clk_set_parent(hws[IMX6SX_PLL7_BYPASS]->clk, hws[IMX6SX_CLK_PLL7]->clk); in imx6sx_clocks_init()
498 clk_set_parent(hws[IMX6SX_CLK_EIM_SLOW_SEL]->clk, hws[IMX6SX_CLK_PLL2_PFD2]->clk); in imx6sx_clocks_init()
506 clk_set_parent(hws[IMX6SX_CLK_LCDIF1_PRE_SEL]->clk, in imx6sx_clocks_init()
508 clk_set_parent(hws[IMX6SX_CLK_LCDIF1_SEL]->clk, in imx6sx_clocks_init()
[all …]
H A Dclk-imx6ul.c179 clk_set_parent(hws[IMX6UL_PLL1_BYPASS]->clk, hws[IMX6UL_CLK_PLL1]->clk); in imx6ul_clocks_init()
180 clk_set_parent(hws[IMX6UL_PLL2_BYPASS]->clk, hws[IMX6UL_CLK_PLL2]->clk); in imx6ul_clocks_init()
181 clk_set_parent(hws[IMX6UL_PLL3_BYPASS]->clk, hws[IMX6UL_CLK_PLL3]->clk); in imx6ul_clocks_init()
182 clk_set_parent(hws[IMX6UL_PLL4_BYPASS]->clk, hws[IMX6UL_CLK_PLL4]->clk); in imx6ul_clocks_init()
183 clk_set_parent(hws[IMX6UL_PLL5_BYPASS]->clk, hws[IMX6UL_CLK_PLL5]->clk); in imx6ul_clocks_init()
184 clk_set_parent(hws[IMX6UL_PLL6_BYPASS]->clk, hws[IMX6UL_CLK_PLL6]->clk); in imx6ul_clocks_init()
185 clk_set_parent(hws[IMX6UL_PLL7_BYPASS]->clk, hws[IMX6UL_CLK_PLL7]->clk); in imx6ul_clocks_init()
513 clk_set_parent(hws[IMX6UL_CLK_PERIPH_CLK2_SEL]->clk, hws[IMX6UL_CLK_OSC]->clk); in imx6ul_clocks_init()
514 clk_set_parent(hws[IMX6UL_CLK_PERIPH]->clk, hws[IMX6UL_CLK_PERIPH_CLK2]->clk); in imx6ul_clocks_init()
515 clk_set_parent(hws[IMX6UL_CLK_PERIPH_PRE]->clk, hws[IMX6UL_CLK_PLL2_BUS]->clk); in imx6ul_clocks_init()
[all …]
H A Dclk-imx6sl.c233 clk_set_parent(hws[IMX6SL_PLL1_BYPASS]->clk, hws[IMX6SL_CLK_PLL1]->clk); in imx6sl_clocks_init()
234 clk_set_parent(hws[IMX6SL_PLL2_BYPASS]->clk, hws[IMX6SL_CLK_PLL2]->clk); in imx6sl_clocks_init()
235 clk_set_parent(hws[IMX6SL_PLL3_BYPASS]->clk, hws[IMX6SL_CLK_PLL3]->clk); in imx6sl_clocks_init()
236 clk_set_parent(hws[IMX6SL_PLL4_BYPASS]->clk, hws[IMX6SL_CLK_PLL4]->clk); in imx6sl_clocks_init()
237 clk_set_parent(hws[IMX6SL_PLL5_BYPASS]->clk, hws[IMX6SL_CLK_PLL5]->clk); in imx6sl_clocks_init()
238 clk_set_parent(hws[IMX6SL_PLL6_BYPASS]->clk, hws[IMX6SL_CLK_PLL6]->clk); in imx6sl_clocks_init()
239 clk_set_parent(hws[IMX6SL_PLL7_BYPASS]->clk, hws[IMX6SL_CLK_PLL7]->clk); in imx6sl_clocks_init()
433 clk_set_parent(hws[IMX6SL_CLK_SPDIF0_SEL]->clk, hws[IMX6SL_CLK_PLL3_PFD3]->clk); in imx6sl_clocks_init()
436 clk_set_parent(hws[IMX6SL_CLK_LCDIF_PIX_SEL]->clk, in imx6sl_clocks_init()
439 clk_set_parent(hws[IMX6SL_CLK_LCDIF_AXI_SEL]->clk, in imx6sl_clocks_init()
H A Dclk-cpu.c50 ret = clk_set_parent(cpu->mux, cpu->step); in clk_cpu_set_rate()
57 clk_set_parent(cpu->mux, cpu->pll); in clk_cpu_set_rate()
61 clk_set_parent(cpu->mux, cpu->pll); in clk_cpu_set_rate()
H A Dclk-imx7d.c868 clk_set_parent(hws[IMX7D_PLL_ARM_MAIN_BYPASS]->clk, hws[IMX7D_PLL_ARM_MAIN]->clk); in imx7d_clocks_init()
869 clk_set_parent(hws[IMX7D_PLL_DRAM_MAIN_BYPASS]->clk, hws[IMX7D_PLL_DRAM_MAIN]->clk); in imx7d_clocks_init()
870 clk_set_parent(hws[IMX7D_PLL_SYS_MAIN_BYPASS]->clk, hws[IMX7D_PLL_SYS_MAIN]->clk); in imx7d_clocks_init()
871 clk_set_parent(hws[IMX7D_PLL_ENET_MAIN_BYPASS]->clk, hws[IMX7D_PLL_ENET_MAIN]->clk); in imx7d_clocks_init()
872 clk_set_parent(hws[IMX7D_PLL_AUDIO_MAIN_BYPASS]->clk, hws[IMX7D_PLL_AUDIO_MAIN]->clk); in imx7d_clocks_init()
873 clk_set_parent(hws[IMX7D_PLL_VIDEO_MAIN_BYPASS]->clk, hws[IMX7D_PLL_VIDEO_MAIN]->clk); in imx7d_clocks_init()
875 clk_set_parent(hws[IMX7D_MIPI_CSI_ROOT_SRC]->clk, hws[IMX7D_PLL_SYS_PFD3_CLK]->clk); in imx7d_clocks_init()
878 clk_set_parent(hws[IMX7D_GPT1_ROOT_SRC]->clk, hws[IMX7D_OSC_24M_CLK]->clk); in imx7d_clocks_init()
H A Dclk-imx6sll.c348 clk_set_parent(hws[IMX6SLL_CLK_PERIPH_CLK2_SEL]->clk, hws[IMX6SLL_CLK_PLL3_USB_OTG]->clk); in imx6sll_clocks_init()
349 clk_set_parent(hws[IMX6SLL_CLK_PERIPH]->clk, hws[IMX6SLL_CLK_PERIPH_CLK2]->clk); in imx6sll_clocks_init()
350 clk_set_parent(hws[IMX6SLL_CLK_PERIPH_PRE]->clk, hws[IMX6SLL_CLK_PLL2_BUS]->clk); in imx6sll_clocks_init()
351 clk_set_parent(hws[IMX6SLL_CLK_PERIPH]->clk, hws[IMX6SLL_CLK_PERIPH_PRE]->clk); in imx6sll_clocks_init()
/linux/sound/soc/mediatek/mt8183/
H A Dmt8183-afe-clk.c134 ret = clk_set_parent(afe_priv->clk[CLK_MUX_AUDIO], in mt8183_afe_enable_clock()
150 ret = clk_set_parent(afe_priv->clk[CLK_MUX_AUDIOINTBUS], in mt8183_afe_enable_clock()
243 ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_1], in apll1_mux_setting()
259 ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_ENG1], in apll1_mux_setting()
268 ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_ENG1], in apll1_mux_setting()
278 ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_1], in apll1_mux_setting()
292 clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_ENG1], in apll1_mux_setting()
297 clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_1], in apll1_mux_setting()
317 ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_2], in apll2_mux_setting()
333 ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_ENG2], in apll2_mux_setting()
[all …]
/linux/drivers/cpufreq/
H A Dtegra124-cpufreq.c41 clk_set_parent(priv->cpu_clk, priv->pllp_clk); in tegra124_cpu_switch_to_dfll()
47 clk_set_parent(priv->cpu_clk, priv->dfll_clk); in tegra124_cpu_switch_to_dfll()
52 clk_set_parent(priv->cpu_clk, orig_parent); in tegra124_cpu_switch_to_dfll()
133 err = clk_set_parent(priv->cpu_clk, priv->pllp_clk); in tegra124_cpufreq_suspend()
159 err = clk_set_parent(priv->cpu_clk, priv->dfll_clk); in tegra124_cpufreq_resume()
H A Dimx6q-cpufreq.c130 clk_set_parent(clks[PLL1_SW].clk, clks[PLL1_SYS].clk); in imx6q_set_target()
132 clk_set_parent(clks[SECONDARY_SEL].clk, in imx6q_set_target()
135 clk_set_parent(clks[SECONDARY_SEL].clk, in imx6q_set_target()
137 clk_set_parent(clks[STEP].clk, clks[SECONDARY_SEL].clk); in imx6q_set_target()
138 clk_set_parent(clks[PLL1_SW].clk, clks[STEP].clk); in imx6q_set_target()
141 clk_set_parent(clks[PLL1_SW].clk, clks[PLL1_SYS].clk); in imx6q_set_target()
144 clk_set_parent(clks[STEP].clk, clks[PLL2_PFD2_396M].clk); in imx6q_set_target()
145 clk_set_parent(clks[PLL1_SW].clk, clks[STEP].clk); in imx6q_set_target()
148 clk_set_parent(clks[PLL1_SW].clk, clks[PLL1_SYS].clk); in imx6q_set_target()
/linux/sound/soc/mediatek/mt8192/
H A Dmt8192-afe-clk.c69 ret = clk_set_parent(afe_priv->clk[CLK_MUX_AUDIOINTBUS], in mt8192_set_audio_int_bus_parent()
92 ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_1], in apll1_mux_setting()
108 ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_ENG1], in apll1_mux_setting()
117 ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_ENG1], in apll1_mux_setting()
127 ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_1], in apll1_mux_setting()
154 ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_2], in apll2_mux_setting()
170 ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_ENG2], in apll2_mux_setting()
179 ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_ENG2], in apll2_mux_setting()
189 ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_2], in apll2_mux_setting()
229 ret = clk_set_parent(afe_priv->clk[CLK_MUX_AUDIO], in mt8192_afe_enable_clock()
[all …]
/linux/sound/soc/samsung/
H A Dsmdk_spdif.c55 clk_set_parent(mout_epll, fout_epll); in set_audio_clock_heirachy()
56 clk_set_parent(sclk_audio0, mout_epll); in set_audio_clock_heirachy()
57 clk_set_parent(sclk_spdif, sclk_audio0); in set_audio_clock_heirachy()
/linux/arch/m68k/coldfire/
H A Dclk.c130 int clk_set_parent(struct clk *clk, struct clk *parent) in clk_set_parent() function
135 EXPORT_SYMBOL(clk_set_parent);
/linux/drivers/clk/ti/
H A Dclk-33xx.c296 clk_set_parent(clk2, clk1); in am33xx_dt_clk_init()
299 clk_set_parent(clk2, clk1); in am33xx_dt_clk_init()
309 clk_set_parent(clk1, clk2); in am33xx_dt_clk_init()
/linux/arch/mips/lantiq/
H A Dclk.c168 int clk_set_parent(struct clk *clk, struct clk *parent) in clk_set_parent() function
172 EXPORT_SYMBOL(clk_set_parent);
/linux/drivers/devfreq/
H A Dimx8m-ddrc.c193 ret = clk_set_parent(priv->dram_core, new_dram_core_parent); in imx8m_ddrc_set_freq()
197 ret = clk_set_parent(priv->dram_alt, new_dram_alt_parent); in imx8m_ddrc_set_freq()
203 ret = clk_set_parent(priv->dram_apb, new_dram_apb_parent); in imx8m_ddrc_set_freq()
/linux/sound/soc/dwc/
H A Ddwc-i2s.c765 ret = clk_set_parent(mclk, mclk_inner); in jh7110_i2s_crg_master_init()
779 ret = clk_set_parent(mclk, mclk_ext); in jh7110_i2s_crg_master_init()
846 ret = clk_set_parent(mclk, mclk_inner); in jh7110_i2s_crg_slave_init()
859 ret = clk_set_parent(bclk, bclk_ext); in jh7110_i2s_crg_slave_init()
863 ret = clk_set_parent(lrck, lrck_ext); in jh7110_i2s_crg_slave_init()
867 ret = clk_set_parent(mclk, mclk_ext); in jh7110_i2s_crg_slave_init()
/linux/arch/arm/mach-spear/
H A Dspear3xx.c93 clk_set_parent(gpt_clk, pclk); in spear3xx_timer_init()
H A Dspear13xx.c120 clk_set_parent(gpt_clk, pclk); in spear13xx_timer_init()
/linux/sound/soc/mediatek/mt2701/
H A Dmt2701-afe-clock-ctrl.c279 ret = clk_set_parent(i2s_path->sel_ck, in mt2701_mclk_configuration()
282 ret = clk_set_parent(i2s_path->sel_ck, in mt2701_mclk_configuration()
/linux/sound/soc/meson/
H A Daxg-tdm-formatter.c208 ret = clk_set_parent(formatter->sclk_sel, ts->iface->sclk); in axg_tdm_formatter_power_up()
213 ret = clk_set_parent(formatter->lrclk_sel, ts->iface->lrclk); in axg_tdm_formatter_power_up()
/linux/drivers/clk/x86/
H A Dclk-fch.c71 clk_set_parent(hws[ST_CLK_MUX]->clk, hws[ST_CLK_48M]->clk); in fch_clk_probe()
/linux/sound/soc/ti/
H A Domap-dmic.c341 ret = clk_set_parent(mux, parent_clk); in omap_dmic_select_fclk()
344 ret = clk_set_parent(mux, parent_clk); in omap_dmic_select_fclk()
/linux/drivers/clk/davinci/
H A Dda8xx-cfgchip.c314 clk_set_parent(mux->hw.clk, parent->clk); in da850_cfgchip_register_async3()
624 clk_set_parent(usb0->hw.clk, parent->clk); in da8xx_cfgchip_register_usb_phy_clk()
638 clk_set_parent(usb1->hw.clk, parent->clk); in da8xx_cfgchip_register_usb_phy_clk()
/linux/sound/soc/mediatek/mt6797/
H A Dmt6797-afe-clk.c83 ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD], in mt6797_afe_enable_clock()
/linux/arch/mips/bcm63xx/
H A Dclk.c392 int clk_set_parent(struct clk *clk, struct clk *parent) in clk_set_parent() function
396 EXPORT_SYMBOL(clk_set_parent);

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