Home
last modified time | relevance | path

Searched refs:clk_rate_khz (Results 1 – 3 of 3) sorted by relevance

/linux/drivers/watchdog/
H A Drzn1_wdt.c37 unsigned long clk_rate_khz; member
40 static inline uint32_t max_heart_beat_ms(unsigned long clk_rate_khz) in max_heart_beat_ms() argument
42 return (RZN1_WDT_MAX * RZN1_WDT_PRESCALER) / clk_rate_khz; in max_heart_beat_ms()
46 unsigned long clk_rate_khz) in compute_reload_value() argument
48 return (tick_ms * clk_rate_khz) / RZN1_WDT_PRESCALER; in compute_reload_value()
76 val |= compute_reload_value(w->max_hw_heartbeat_ms, wdt->clk_rate_khz); in rzn1_wdt_start()
142 wdt->clk_rate_khz = clk_rate / 1000; in rzn1_wdt_probe()
154 wdt->wdtdev.max_hw_heartbeat_ms = max_heart_beat_ms(wdt->clk_rate_khz); in rzn1_wdt_probe()
H A Drealtek_otto_wdt.c70 unsigned int clk_rate_khz; member
109 return DIV_ROUND_CLOSEST(1 << (25 + prescale), ctrl->clk_rate_khz); in otto_wdt_tick_ms()
246 ctrl->clk_rate_khz = clk_get_rate(clk) / 1000; in otto_wdt_probe_clk()
247 if (ctrl->clk_rate_khz == 0) in otto_wdt_probe_clk()
/linux/drivers/i2c/busses/
H A Di2c-hisi.c87 #define NSEC_TO_CYCLES(ns, clk_rate_khz) \ argument
88 DIV_ROUND_UP_ULL((clk_rate_khz) * (ns), NSEC_PER_MSEC)
110 u32 clk_rate_khz; member
397 total_cnt = DIV_ROUND_UP_ULL(ctlr->clk_rate_khz * HZ_PER_KHZ, ctlr->t.bus_freq_hz); in hisi_i2c_set_scl()
403 scl_fall_cnt = NSEC_TO_CYCLES(ctlr->t.scl_fall_ns, ctlr->clk_rate_khz); in hisi_i2c_set_scl()
405 scl_rise_cnt = NSEC_TO_CYCLES(ctlr->t.scl_rise_ns, ctlr->clk_rate_khz); in hisi_i2c_set_scl()
420 ctlr->spk_len = NSEC_TO_CYCLES(ctlr->t.digital_filter_width_ns, ctlr->clk_rate_khz); in hisi_i2c_configure_bus()
446 sda_hold_cnt = NSEC_TO_CYCLES(ctlr->t.sda_hold_ns, ctlr->clk_rate_khz); in hisi_i2c_configure_bus()
496 ctlr->clk_rate_khz = DIV_ROUND_UP_ULL(clk_rate_hz, HZ_PER_KHZ); in hisi_i2c_probe()