| /linux/drivers/mtd/nand/raw/ |
| H A D | cadence-nand-controller.c | 2379 static inline u32 calc_tdvw_max(u32 trp_cnt, u32 clk_period, u32 trhoh_min, in calc_tdvw_max() argument
2383 clk_period /= 2; in calc_tdvw_max()
2385 return (trp_cnt + 1) * clk_period + trhoh_min + in calc_tdvw_max()
2390 static inline u32 calc_tdvw(u32 trp_cnt, u32 clk_period, u32 trhoh_min, in calc_tdvw() argument
2394 clk_period /= 2; in calc_tdvw()
2396 return (trp_cnt + 1) * clk_period + trhoh_min - trea_max; in calc_tdvw()
2407 u32 clk_period = DIV_ROUND_DOWN_ULL(1000000000000ULL, in cadence_nand_setup_sdr_interface() local
2429 dqs_sampl_res = clk_period / phony_dqs_mod; in cadence_nand_setup_sdr_interface()
2441 if (sdr->tRC_min <= clk_period && in cadence_nand_setup_sdr_interface()
2442 sdr->tRP_min <= (clk_period / 2) && in cadence_nand_setup_sdr_interface()
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| /linux/drivers/memory/ |
| H A D | jz4780-nemc.c | 56 uint32_t clk_period; member
155 return ((ns * 1000) + nemc->clk_period - 1) / nemc->clk_period; in jz4780_nemc_ns_to_cycles()
327 nemc->clk_period = jz4780_nemc_clk_period(nemc); in jz4780_nemc_probe()
328 if (!nemc->clk_period) { in jz4780_nemc_probe()
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| H A D | stm32-fmc2-ebi.c | 426 u32 bcr, btr, clk_period; in stm32_fmc2_ebi_ns_to_clk_period() local
440 clk_period = FIELD_GET(FMC2_BTR_CLKDIV, btr) + 1; in stm32_fmc2_ebi_ns_to_clk_period()
442 return DIV_ROUND_UP(nb_clk_cycles, clk_period); in stm32_fmc2_ebi_ns_to_clk_period()
449 u32 cfgr, btr, clk_period; in stm32_fmc2_ebi_mp25_ns_to_clk_period() local
457 clk_period = FIELD_GET(FMC2_CFGR_CLKDIV, cfgr) + 1; in stm32_fmc2_ebi_mp25_ns_to_clk_period()
463 clk_period = FIELD_GET(FMC2_BTR_CLKDIV, btr) + 1; in stm32_fmc2_ebi_mp25_ns_to_clk_period()
466 return DIV_ROUND_UP(nb_clk_cycles, clk_period); in stm32_fmc2_ebi_mp25_ns_to_clk_period()
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| /linux/include/linux/ |
| H A D | tc.h | 52 s32 clk_period; /* Clock period in nanoseconds. */ member
118 return 100000 * (10000 / (unsigned long)tbus->info.clk_period); in tc_get_speed()
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| /linux/drivers/i2c/busses/ |
| H A D | i2c-img-scb.c | 1151 unsigned int clk_khz, bitrate_khz, clk_period, tckh, tckl, tsdh; in img_i2c_init() local
1231 clk_period = (256 * 1000000) / (clk_khz * inc); in img_i2c_init()
1234 int_bitrate = 1000000 / (bitrate_khz * clk_period); in img_i2c_init()
1235 if ((1000000 % (bitrate_khz * clk_period)) >= in img_i2c_init()
1236 ((bitrate_khz * clk_period) / 2)) in img_i2c_init()
1247 data = DIV_ROUND_UP(timing.tckl, clk_period); in img_i2c_init()
1264 tsdh = DIV_ROUND_UP(timing.tsdh, clk_period); in img_i2c_init()
1276 data = timing.tpl / clk_period; in img_i2c_init()
1282 data = timing.tph / clk_period; in img_i2c_init()
1291 data = timing.tp2s / clk_period; in img_i2c_init()
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| /linux/drivers/video/fbdev/omap/ |
| H A D | sossi.c | 116 u32 clk_period = HZ_TO_PS(sossi.fck_hz) * div; in ps_to_sossi_ticks() local
117 return (clk_period + ps - 1) / clk_period; in ps_to_sossi_ticks()
351 static void sossi_get_clk_info(u32 *clk_period, u32 *max_clk_div) in sossi_get_clk_info() argument
353 *clk_period = HZ_TO_PS(sossi.fck_hz); in sossi_get_clk_info()
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| H A D | omapfb.h | 113 void (*get_clk_info) (u32 *clk_period, u32 *max_clk_div);
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| /linux/drivers/net/ethernet/microchip/sparx5/ |
| H A D | sparx5_main.c | 483 u32 clk_div, clk_period, pol_upd_int, idx; in sparx5_init_coreclock() local
584 clk_period = sparx5_clk_period(freq); in sparx5_init_coreclock()
587 spx5_rmw(HSCH_SYS_CLK_PER_100PS_SET(clk_period / 100), in sparx5_init_coreclock()
592 spx5_rmw(ANA_AC_POL_BDLB_DLB_CTRL_CLK_PERIOD_01NS_SET(clk_period / 100), in sparx5_init_coreclock()
597 spx5_rmw(ANA_AC_POL_SLB_DLB_CTRL_CLK_PERIOD_01NS_SET(clk_period / 100), in sparx5_init_coreclock()
602 spx5_rmw(LRN_AUTOAGE_CFG_1_CLK_PERIOD_01NS_SET(clk_period / 100), in sparx5_init_coreclock()
608 spx5_rmw(GCB_SIO_CLOCK_SYS_CLK_PERIOD_SET(clk_period / 100), in sparx5_init_coreclock()
614 ((256 * 1000) / clk_period), in sparx5_init_coreclock()
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| /linux/drivers/mmc/host/ |
| H A D | cavium.c | 826 int clk_period = 0, power_class = 10, bus_width = 0; in cvm_mmc_set_ios() local
877 clk_period = (host->sys_freq + clock - 1) / (2 * clock); in cvm_mmc_set_ios()
883 FIELD_PREP(MIO_EMM_SWITCH_CLK_HI, clk_period) | in cvm_mmc_set_ios()
884 FIELD_PREP(MIO_EMM_SWITCH_CLK_LO, clk_period); in cvm_mmc_set_ios()
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