/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/ |
H A D | dcn401_clk_mgr.c | 209 void dcn401_init_clocks(struct clk_mgr *clk_mgr_base) in dcn401_init_clocks() argument 211 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); in dcn401_init_clocks() 215 if (!clk_mgr_base->bw_params) in dcn401_init_clocks() 218 num_entries_per_clk = &clk_mgr_base->bw_params->clk_table.num_entries_per_clk; in dcn401_init_clocks() 220 memset(&(clk_mgr_base->clks), 0, sizeof(struct dc_clocks)); in dcn401_init_clocks() 221 clk_mgr_base->clks.p_state_change_support = true; in dcn401_init_clocks() 222 clk_mgr_base->clks.prev_p_state_change_support = true; in dcn401_init_clocks() 223 clk_mgr_base->clks.fclk_prev_p_state_change_support = true; in dcn401_init_clocks() 227 if (!clk_mgr_base->force_smu_not_present && dcn30_smu_get_smu_version(clk_mgr, &clk_mgr->smu_ver)) in dcn401_init_clocks() 238 &clk_mgr_base->bw_params->clk_table.entries[0].dcfclk_mhz, in dcn401_init_clocks() [all …]
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/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/ |
H A D | dcn30_clk_mgr.c | 108 void dcn3_init_clocks(struct clk_mgr *clk_mgr_base) in dcn3_init_clocks() argument 110 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); in dcn3_init_clocks() 113 memset(&(clk_mgr_base->clks), 0, sizeof(struct dc_clocks)); in dcn3_init_clocks() 114 clk_mgr_base->clks.p_state_change_support = true; in dcn3_init_clocks() 115 clk_mgr_base->clks.prev_p_state_change_support = true; in dcn3_init_clocks() 118 if (!clk_mgr_base->bw_params) in dcn3_init_clocks() 121 if (!clk_mgr_base->force_smu_not_present && dcn30_smu_get_smu_version(clk_mgr, &clk_mgr->smu_ver)) in dcn3_init_clocks() 133 &clk_mgr_base->bw_params->clk_table.entries[0].dcfclk_mhz, in dcn3_init_clocks() 139 &clk_mgr_base->bw_params->clk_table.entries[0].dtbclk_mhz, in dcn3_init_clocks() 144 &clk_mgr_base->bw_params->clk_table.entries[0].socclk_mhz, in dcn3_init_clocks() [all …]
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/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/ |
H A D | dcn32_clk_mgr.c | 162 void dcn32_init_clocks(struct clk_mgr *clk_mgr_base) in dcn32_init_clocks() argument 164 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); in dcn32_init_clocks() 169 if (!clk_mgr_base->bw_params) in dcn32_init_clocks() 172 num_entries_per_clk = &clk_mgr_base->bw_params->clk_table.num_entries_per_clk; in dcn32_init_clocks() 174 memset(&(clk_mgr_base->clks), 0, sizeof(struct dc_clocks)); in dcn32_init_clocks() 175 clk_mgr_base->clks.p_state_change_support = true; in dcn32_init_clocks() 176 clk_mgr_base->clks.prev_p_state_change_support = true; in dcn32_init_clocks() 177 clk_mgr_base->clks.fclk_prev_p_state_change_support = true; in dcn32_init_clocks() 181 if (!clk_mgr_base->force_smu_not_present && dcn30_smu_get_smu_version(clk_mgr, &clk_mgr->smu_ver)) in dcn32_init_clocks() 192 &clk_mgr_base->bw_params->clk_table.entries[0].dcfclk_mhz, in dcn32_init_clocks() [all …]
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H A D | dcn32_clk_mgr.h | 28 void dcn32_init_clocks(struct clk_mgr *clk_mgr_base);
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/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn201/ |
H A D | dcn201_clk_mgr.c | 84 static void dcn201_update_clocks(struct clk_mgr *clk_mgr_base, in dcn201_update_clocks() argument 88 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); in dcn201_update_clocks() 90 struct dc *dc = clk_mgr_base->ctx->dc; in dcn201_update_clocks() 101 if (clk_mgr_base->clks.dispclk_khz == 0 || in dcn201_update_clocks() 113 dcn2_read_clocks_from_hw_dentist(clk_mgr_base); in dcn201_update_clocks() 116 if (should_set_clock(safe_to_lower, new_clocks->phyclk_khz, clk_mgr_base->clks.phyclk_khz)) in dcn201_update_clocks() 117 clk_mgr_base->clks.phyclk_khz = new_clocks->phyclk_khz; in dcn201_update_clocks() 123 if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr_base->clks.dcfclk_khz)) in dcn201_update_clocks() 124 clk_mgr_base->clks.dcfclk_khz = new_clocks->dcfclk_khz; in dcn201_update_clocks() 127 new_clocks->dcfclk_deep_sleep_khz, clk_mgr_base->clks.dcfclk_deep_sleep_khz)) in dcn201_update_clocks() [all …]
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/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/ |
H A D | rn_clk_mgr.c | 86 static void rn_set_low_power_state(struct clk_mgr *clk_mgr_base) in rn_set_low_power_state() argument 89 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); in rn_set_low_power_state() 90 struct dc *dc = clk_mgr_base->ctx->dc; in rn_set_low_power_state() 93 if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_LOW_POWER) { in rn_set_low_power_state() 101 clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_LOW_POWER; in rn_set_low_power_state() 131 static void rn_update_clocks(struct clk_mgr *clk_mgr_base, in rn_update_clocks() argument 135 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); in rn_update_clocks() 137 struct dc *dc = clk_mgr_base->ctx->dc; in rn_update_clocks() 143 struct dmcu *dmcu = clk_mgr_base->ctx->dc->res_pool->dmcu; in rn_update_clocks() 154 if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_LOW_POWER) { in rn_update_clocks() [all …]
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/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/ |
H A D | dcn20_clk_mgr.c | 216 void dcn2_update_clocks(struct clk_mgr *clk_mgr_base, in dcn2_update_clocks() argument 220 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); in dcn2_update_clocks() 222 struct dc *dc = clk_mgr_base->ctx->dc; in dcn2_update_clocks() 229 struct dmcu *dmcu = clk_mgr_base->ctx->dc->res_pool->dmcu; in dcn2_update_clocks() 237 if (clk_mgr_base->clks.dispclk_khz == 0 || in dcn2_update_clocks() 242 dcn2_read_clocks_from_hw_dentist(clk_mgr_base); in dcn2_update_clocks() 262 if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr_base->clks.dcfclk_khz)) { in dcn2_update_clocks() 263 clk_mgr_base->clks.dcfclk_khz = new_clocks->dcfclk_khz; in dcn2_update_clocks() 265 …pp_smu->set_hard_min_dcfclk_by_freq(&pp_smu->pp_smu, khz_to_mhz_ceil(clk_mgr_base->clks.dcfclk_khz… in dcn2_update_clocks() 269 new_clocks->dcfclk_deep_sleep_khz, clk_mgr_base->clks.dcfclk_deep_sleep_khz)) { in dcn2_update_clocks() [all …]
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H A D | dcn20_clk_mgr.h | 56 void dcn2_read_clocks_from_hw_dentist(struct clk_mgr *clk_mgr_base);
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/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/ |
H A D | rv1_clk_mgr.c | 187 static void rv1_update_clocks(struct clk_mgr *clk_mgr_base, in rv1_update_clocks() argument 191 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); in rv1_update_clocks() 192 struct dc *dc = clk_mgr_base->ctx->dc; in rv1_update_clocks() 224 if (new_clocks->dispclk_khz > clk_mgr_base->clks.dispclk_khz in rv1_update_clocks() 225 || new_clocks->phyclk_khz > clk_mgr_base->clks.phyclk_khz in rv1_update_clocks() 226 || new_clocks->fclk_khz > clk_mgr_base->clks.fclk_khz in rv1_update_clocks() 227 || new_clocks->dcfclk_khz > clk_mgr_base->clks.dcfclk_khz) in rv1_update_clocks() 230 if (should_set_clock(safe_to_lower, new_clocks->phyclk_khz, clk_mgr_base->clks.phyclk_khz)) { in rv1_update_clocks() 231 clk_mgr_base->clks.phyclk_khz = new_clocks->phyclk_khz; in rv1_update_clocks() 239 if (should_set_clock(safe_to_lower, new_clocks->fclk_khz, clk_mgr_base->clks.fclk_khz)) { in rv1_update_clocks() [all …]
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/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/ |
H A D | dcn316_clk_mgr.c | 102 static void dcn316_disable_otg_wa(struct clk_mgr *clk_mgr_base, struct dc_state *context, in dcn316_disable_otg_wa() argument 105 struct dc *dc = clk_mgr_base->ctx->dc; in dcn316_disable_otg_wa() 128 static void dcn316_enable_pme_wa(struct clk_mgr *clk_mgr_base) in dcn316_enable_pme_wa() argument 130 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); in dcn316_enable_pme_wa() 135 static void dcn316_update_clocks(struct clk_mgr *clk_mgr_base, in dcn316_update_clocks() argument 140 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); in dcn316_update_clocks() 142 struct dc *dc = clk_mgr_base->ctx->dc; in dcn316_update_clocks() 155 clk_mgr_base->clks.zstate_support = new_clocks->zstate_support; in dcn316_update_clocks() 157 if (clk_mgr_base->clks.dtbclk_en && !new_clocks->dtbclk_en) { in dcn316_update_clocks() 159 clk_mgr_base->clks.dtbclk_en = new_clocks->dtbclk_en; in dcn316_update_clocks() [all …]
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/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/ |
H A D | dcn315_clk_mgr.c | 100 static void dcn315_disable_otg_wa(struct clk_mgr *clk_mgr_base, struct dc_state *context, bool disa… in dcn315_disable_otg_wa() argument 102 struct dc *dc = clk_mgr_base->ctx->dc; in dcn315_disable_otg_wa() 125 static void dcn315_update_clocks(struct clk_mgr *clk_mgr_base, in dcn315_update_clocks() argument 130 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); in dcn315_update_clocks() 132 struct dc *dc = clk_mgr_base->ctx->dc; in dcn315_update_clocks() 141 clk_mgr_base->clks.zstate_support = new_clocks->zstate_support; in dcn315_update_clocks() 146 clk_mgr_base->clks.zstate_support = new_clocks->zstate_support; in dcn315_update_clocks() 148 if (clk_mgr_base->clks.dtbclk_en && !new_clocks->dtbclk_en) { in dcn315_update_clocks() 150 clk_mgr_base->clks.dtbclk_en = new_clocks->dtbclk_en; in dcn315_update_clocks() 153 if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_LOW_POWER) { in dcn315_update_clocks() [all …]
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/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dce120/ |
H A D | dce120_clk_mgr.c | 84 static void dce12_update_clocks(struct clk_mgr *clk_mgr_base, in dce12_update_clocks() argument 88 struct clk_mgr_internal *clk_mgr_dce = TO_CLK_MGR_INTERNAL(clk_mgr_base); in dce12_update_clocks() 97 if (should_set_clock(safe_to_lower, patched_disp_clk, clk_mgr_base->clks.dispclk_khz)) { in dce12_update_clocks() 107 clk_mgr_base->clks.dispclk_khz = dce112_set_clock(clk_mgr_base, patched_disp_clk); in dce12_update_clocks() 109 dm_pp_apply_clock_for_voltage_request(clk_mgr_base->ctx, &clock_voltage_req); in dce12_update_clocks() 112 if (should_set_clock(safe_to_lower, max_pix_clk, clk_mgr_base->clks.phyclk_khz)) { in dce12_update_clocks() 115 clk_mgr_base->clks.phyclk_khz = max_pix_clk; in dce12_update_clocks() 117 dm_pp_apply_clock_for_voltage_request(clk_mgr_base->ctx, &clock_voltage_req); in dce12_update_clocks() 119 dce11_pplib_apply_display_requirements(clk_mgr_base->ctx->dc, context); in dce12_update_clocks()
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/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/ |
H A D | dce112_clk_mgr.c | 70 int dce112_set_clock(struct clk_mgr *clk_mgr_base, int requested_clk_khz) in dce112_set_clock() argument 72 struct clk_mgr_internal *clk_mgr_dce = TO_CLK_MGR_INTERNAL(clk_mgr_base); in dce112_set_clock() 74 struct dc_bios *bp = clk_mgr_base->ctx->dc_bios; in dce112_set_clock() 75 struct dc *dc = clk_mgr_base->ctx->dc; in dce112_set_clock() 104 if (!((clk_mgr_base->ctx->asic_id.chip_family == FAMILY_AI) && in dce112_set_clock() 105 ASICREV_IS_VEGA20_P(clk_mgr_base->ctx->asic_id.hw_internal_rev))) in dce112_set_clock() 191 static void dce112_update_clocks(struct clk_mgr *clk_mgr_base, in dce112_update_clocks() argument 195 struct clk_mgr_internal *clk_mgr_dce = TO_CLK_MGR_INTERNAL(clk_mgr_base); in dce112_update_clocks() 203 level_change_req.power_level = dce_get_required_clocks_state(clk_mgr_base, context); in dce112_update_clocks() 207 if (dm_pp_apply_power_level_change_request(clk_mgr_base->ctx, &level_change_req)) in dce112_update_clocks() [all …]
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H A D | dce112_clk_mgr.h | 35 int dce112_set_clock(struct clk_mgr *clk_mgr_base, int requested_clk_khz);
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/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dce60/ |
H A D | dce60_clk_mgr.c | 83 static int dce60_get_dp_ref_freq_khz(struct clk_mgr *clk_mgr_base) in dce60_get_dp_ref_freq_khz() argument 85 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); in dce60_get_dp_ref_freq_khz() 120 static void dce60_update_clocks(struct clk_mgr *clk_mgr_base, in dce60_update_clocks() argument 124 struct clk_mgr_internal *clk_mgr_dce = TO_CLK_MGR_INTERNAL(clk_mgr_base); in dce60_update_clocks() 132 level_change_req.power_level = dce_get_required_clocks_state(clk_mgr_base, context); in dce60_update_clocks() 136 if (dm_pp_apply_power_level_change_request(clk_mgr_base->ctx, &level_change_req)) in dce60_update_clocks() 140 if (should_set_clock(safe_to_lower, patched_disp_clk, clk_mgr_base->clks.dispclk_khz)) { in dce60_update_clocks() 141 patched_disp_clk = dce_set_clock(clk_mgr_base, patched_disp_clk); in dce60_update_clocks() 142 clk_mgr_base->clks.dispclk_khz = patched_disp_clk; in dce60_update_clocks() 144 dce60_pplib_apply_display_requirements(clk_mgr_base->ctx->dc, context); in dce60_update_clocks()
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/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/ |
H A D | dcn35_clk_mgr.c | 124 static void dcn35_disable_otg_wa(struct clk_mgr *clk_mgr_base, struct dc_state *context, in dcn35_disable_otg_wa() argument 127 struct dc *dc = clk_mgr_base->ctx->dc; in dcn35_disable_otg_wa() 136 struct clk_mgr_internal *clk_mgr_internal = TO_CLK_MGR_INTERNAL(clk_mgr_base); in dcn35_disable_otg_wa() 269 static void dcn35_notify_host_router_bw(struct clk_mgr *clk_mgr_base, struct dc_state *context, in dcn35_notify_host_router_bw() argument 273 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); in dcn35_notify_host_router_bw() 298 …if (should_set_clock(safe_to_lower, new_clocks->host_router_bw_kbps[i], clk_mgr_base->clks.host_ro… in dcn35_notify_host_router_bw() 299 clk_mgr_base->clks.host_router_bw_kbps[i] = new_clocks->host_router_bw_kbps[i]; in dcn35_notify_host_router_bw() 305 void dcn35_update_clocks(struct clk_mgr *clk_mgr_base, in dcn35_update_clocks() argument 310 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); in dcn35_update_clocks() 312 struct dc *dc = clk_mgr_base->ctx->dc; in dcn35_update_clocks() [all …]
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H A D | dcn35_clk_mgr.h | 52 void dcn35_update_clocks(struct clk_mgr *clk_mgr_base,
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/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/ |
H A D | dce_clk_mgr.c | 129 int dce_get_dp_ref_freq_khz(struct clk_mgr *clk_mgr_base) in dce_get_dp_ref_freq_khz() argument 131 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); in dce_get_dp_ref_freq_khz() 155 int dce12_get_dp_ref_freq_khz(struct clk_mgr *clk_mgr_base) in dce12_get_dp_ref_freq_khz() argument 157 struct clk_mgr_internal *clk_mgr_dce = TO_CLK_MGR_INTERNAL(clk_mgr_base); in dce12_get_dp_ref_freq_khz() 159 return dce_adjust_dp_ref_freq_for_ss(clk_mgr_dce, clk_mgr_base->dprefclk_khz); in dce12_get_dp_ref_freq_khz() 195 struct clk_mgr *clk_mgr_base, in dce_get_required_clocks_state() argument 198 struct clk_mgr_internal *clk_mgr_dce = TO_CLK_MGR_INTERNAL(clk_mgr_base); in dce_get_required_clocks_state() 230 struct clk_mgr *clk_mgr_base, in dce_set_clock() argument 233 struct clk_mgr_internal *clk_mgr_dce = TO_CLK_MGR_INTERNAL(clk_mgr_base); in dce_set_clock() 235 struct dc_bios *bp = clk_mgr_base->ctx->dc_bios; in dce_set_clock() [all …]
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H A D | dce_clk_mgr.h | 34 int dce_get_dp_ref_freq_khz(struct clk_mgr *clk_mgr_base); 36 struct clk_mgr *clk_mgr_base, 51 struct clk_mgr *clk_mgr_base,
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/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/ |
H A D | vg_clk_mgr.c | 95 static void vg_update_clocks(struct clk_mgr *clk_mgr_base, in vg_update_clocks() argument 99 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); in vg_update_clocks() 101 struct dc *dc = clk_mgr_base->ctx->dc; in vg_update_clocks() 116 if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_LOW_POWER) { in vg_update_clocks() 128 clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_LOW_POWER; in vg_update_clocks() 133 if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_MISSION_MODE) { in vg_update_clocks() 138 clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_MISSION_MODE; in vg_update_clocks() 142 …if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr_base->clks.dcfclk_khz) && !dc-… in vg_update_clocks() 143 clk_mgr_base->clks.dcfclk_khz = new_clocks->dcfclk_khz; in vg_update_clocks() 144 dcn301_smu_set_hard_min_dcfclk(clk_mgr, clk_mgr_base->clks.dcfclk_khz); in vg_update_clocks() [all …]
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/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/ |
H A D | dce110_clk_mgr.c | 249 static void dce11_update_clocks(struct clk_mgr *clk_mgr_base, in dce11_update_clocks() argument 253 struct clk_mgr_internal *clk_mgr_dce = TO_CLK_MGR_INTERNAL(clk_mgr_base); in dce11_update_clocks() 261 level_change_req.power_level = dce_get_required_clocks_state(clk_mgr_base, context); in dce11_update_clocks() 265 if (dm_pp_apply_power_level_change_request(clk_mgr_base->ctx, &level_change_req)) in dce11_update_clocks() 269 if (should_set_clock(safe_to_lower, patched_disp_clk, clk_mgr_base->clks.dispclk_khz)) { in dce11_update_clocks() 270 context->bw_ctx.bw.dce.dispclk_khz = dce_set_clock(clk_mgr_base, patched_disp_clk); in dce11_update_clocks() 271 clk_mgr_base->clks.dispclk_khz = patched_disp_clk; in dce11_update_clocks() 273 dce11_pplib_apply_display_requirements(clk_mgr_base->ctx->dc, context); in dce11_update_clocks()
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/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/ |
H A D | clk_mgr.c | 384 void dc_destroy_clk_mgr(struct clk_mgr *clk_mgr_base) in dc_destroy_clk_mgr() argument 386 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); in dc_destroy_clk_mgr() 389 switch (clk_mgr_base->ctx->asic_id.chip_family) { in dc_destroy_clk_mgr() 391 if (ASICREV_IS_SIENNA_CICHLID_P(clk_mgr_base->ctx->asic_id.hw_internal_rev)) { in dc_destroy_clk_mgr() 393 } else if (ASICREV_IS_DIMGREY_CAVEFISH_P(clk_mgr_base->ctx->asic_id.hw_internal_rev)) { in dc_destroy_clk_mgr() 396 if (ASICREV_IS_BEIGE_GOBY_P(clk_mgr_base->ctx->asic_id.hw_internal_rev)) { in dc_destroy_clk_mgr() 402 if (ASICREV_IS_VANGOGH(clk_mgr_base->ctx->asic_id.hw_internal_rev)) in dc_destroy_clk_mgr()
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/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/ |
H A D | dcn31_clk_mgr.h | 45 void dcn31_update_clocks(struct clk_mgr *clk_mgr_base, 54 int dcn31_get_dtb_ref_freq_khz(struct clk_mgr *clk_mgr_base);
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/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/ |
H A D | dcn314_clk_mgr.h | 53 bool dcn314_is_spll_ssc_enabled(struct clk_mgr *clk_mgr_base); 57 void dcn314_update_clocks(struct clk_mgr *clk_mgr_base,
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/linux/drivers/gpu/drm/amd/display/dc/inc/hw/ |
H A D | clk_mgr.h | 288 struct clk_mgr *clk_mgr_base, struct clk_log_info *log_info); 322 int (*get_dispclk_from_dentist)(struct clk_mgr *clk_mgr_base);
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