Home
last modified time | relevance | path

Searched refs:clk_mgr_base (Results 1 – 22 of 22) sorted by relevance

/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/
H A Ddcn30_clk_mgr.c109 void dcn3_init_clocks(struct clk_mgr *clk_mgr_base) in dcn3_init_clocks() argument
111 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); in dcn3_init_clocks()
114 memset(&(clk_mgr_base->clks), 0, sizeof(struct dc_clocks)); in dcn3_init_clocks()
115 clk_mgr_base->clks.p_state_change_support = true; in dcn3_init_clocks()
116 clk_mgr_base->clks.prev_p_state_change_support = true; in dcn3_init_clocks()
119 if (!clk_mgr_base->bw_params) in dcn3_init_clocks()
122 if (!clk_mgr_base->force_smu_not_present && dcn30_smu_get_smu_version(clk_mgr, &clk_mgr->smu_ver)) in dcn3_init_clocks()
134 &clk_mgr_base->bw_params->clk_table.entries[0].dcfclk_mhz, in dcn3_init_clocks()
140 &clk_mgr_base->bw_params->clk_table.entries[0].dtbclk_mhz, in dcn3_init_clocks()
145 &clk_mgr_base->bw_params->clk_table.entries[0].socclk_mhz, in dcn3_init_clocks()
[all …]
H A Ddcn30m_clk_mgr.c31 uint32_t dcn30m_set_smartmux_switch(struct clk_mgr *clk_mgr_base, uint32_t pins_to_set) in dcn30m_set_smartmux_switch() argument
33 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); in dcn30m_set_smartmux_switch()
H A Ddcn30m_clk_mgr.h29 uint32_t dcn30m_set_smartmux_switch(struct clk_mgr *clk_mgr_base, uint32_t pins_to_set);
H A Ddcn30_clk_mgr.h89 void dcn3_init_clocks(struct clk_mgr *clk_mgr_base);
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/
H A Ddcn401_clk_mgr.c216 void dcn401_init_clocks(struct clk_mgr *clk_mgr_base) in dcn401_init_clocks() argument
218 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); in dcn401_init_clocks()
222 if (!clk_mgr_base->bw_params) in dcn401_init_clocks()
225 num_entries_per_clk = &clk_mgr_base->bw_params->clk_table.num_entries_per_clk; in dcn401_init_clocks()
227 memset(&(clk_mgr_base->clks), 0, sizeof(struct dc_clocks)); in dcn401_init_clocks()
228 clk_mgr_base->clks.p_state_change_support = true; in dcn401_init_clocks()
229 clk_mgr_base->clks.prev_p_state_change_support = true; in dcn401_init_clocks()
230 clk_mgr_base->clks.fclk_prev_p_state_change_support = true; in dcn401_init_clocks()
234 if (!clk_mgr_base->force_smu_not_present && dcn401_smu_get_smu_version(clk_mgr, &clk_mgr->smu_ver)) in dcn401_init_clocks()
245 &clk_mgr_base->bw_params->clk_table.entries[0].dcfclk_mhz, in dcn401_init_clocks()
[all …]
H A Ddcn401_clk_mgr.h107 void dcn401_init_clocks(struct clk_mgr *clk_mgr_base);
108 bool dcn401_is_dc_mode_present(struct clk_mgr *clk_mgr_base);
115 unsigned int dcn401_get_max_clock_khz(struct clk_mgr *clk_mgr_base, enum clk_type clk_type);
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/
H A Ddcn32_clk_mgr.c162 void dcn32_init_clocks(struct clk_mgr *clk_mgr_base) in dcn32_init_clocks() argument
164 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); in dcn32_init_clocks()
169 if (!clk_mgr_base->bw_params) in dcn32_init_clocks()
172 num_entries_per_clk = &clk_mgr_base->bw_params->clk_table.num_entries_per_clk; in dcn32_init_clocks()
174 memset(&(clk_mgr_base->clks), 0, sizeof(struct dc_clocks)); in dcn32_init_clocks()
175 clk_mgr_base->clks.p_state_change_support = true; in dcn32_init_clocks()
176 clk_mgr_base->clks.prev_p_state_change_support = true; in dcn32_init_clocks()
177 clk_mgr_base->clks.fclk_prev_p_state_change_support = true; in dcn32_init_clocks()
181 if (!clk_mgr_base->force_smu_not_present && dcn30_smu_get_smu_version(clk_mgr, &clk_mgr->smu_ver)) in dcn32_init_clocks()
192 &clk_mgr_base->bw_params->clk_table.entries[0].dcfclk_mhz, in dcn32_init_clocks()
[all …]
H A Ddcn32_clk_mgr.h28 void dcn32_init_clocks(struct clk_mgr *clk_mgr_base);
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn201/
H A Ddcn201_clk_mgr.c84 static void dcn201_update_clocks(struct clk_mgr *clk_mgr_base, in dcn201_update_clocks() argument
88 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); in dcn201_update_clocks()
90 struct dc *dc = clk_mgr_base->ctx->dc; in dcn201_update_clocks()
101 if (clk_mgr_base->clks.dispclk_khz == 0 || in dcn201_update_clocks()
113 dcn2_read_clocks_from_hw_dentist(clk_mgr_base); in dcn201_update_clocks()
116 if (should_set_clock(safe_to_lower, new_clocks->phyclk_khz, clk_mgr_base->clks.phyclk_khz)) in dcn201_update_clocks()
117 clk_mgr_base->clks.phyclk_khz = new_clocks->phyclk_khz; in dcn201_update_clocks()
123 if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr_base->clks.dcfclk_khz)) in dcn201_update_clocks()
124 clk_mgr_base->clks.dcfclk_khz = new_clocks->dcfclk_khz; in dcn201_update_clocks()
127 new_clocks->dcfclk_deep_sleep_khz, clk_mgr_base->clks.dcfclk_deep_sleep_khz)) in dcn201_update_clocks()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/
H A Drn_clk_mgr.c86 static void rn_set_low_power_state(struct clk_mgr *clk_mgr_base) in rn_set_low_power_state() argument
89 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); in rn_set_low_power_state()
90 struct dc *dc = clk_mgr_base->ctx->dc; in rn_set_low_power_state()
93 if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_LOW_POWER) { in rn_set_low_power_state()
101 clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_LOW_POWER; in rn_set_low_power_state()
131 static void rn_update_clocks(struct clk_mgr *clk_mgr_base, in rn_update_clocks() argument
135 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); in rn_update_clocks()
137 struct dc *dc = clk_mgr_base->ctx->dc; in rn_update_clocks()
143 struct dmcu *dmcu = clk_mgr_base->ctx->dc->res_pool->dmcu; in rn_update_clocks()
154 if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_LOW_POWER) { in rn_update_clocks()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/
H A Ddcn20_clk_mgr.c216 void dcn2_update_clocks(struct clk_mgr *clk_mgr_base, in dcn2_update_clocks() argument
220 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); in dcn2_update_clocks()
222 struct dc *dc = clk_mgr_base->ctx->dc; in dcn2_update_clocks()
229 struct dmcu *dmcu = clk_mgr_base->ctx->dc->res_pool->dmcu; in dcn2_update_clocks()
237 if (clk_mgr_base->clks.dispclk_khz == 0 || in dcn2_update_clocks()
242 dcn2_read_clocks_from_hw_dentist(clk_mgr_base); in dcn2_update_clocks()
262 if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr_base->clks.dcfclk_khz)) { in dcn2_update_clocks()
263 clk_mgr_base->clks.dcfclk_khz = new_clocks->dcfclk_khz; in dcn2_update_clocks()
265 …pp_smu->set_hard_min_dcfclk_by_freq(&pp_smu->pp_smu, khz_to_mhz_ceil(clk_mgr_base->clks.dcfclk_khz… in dcn2_update_clocks()
269 new_clocks->dcfclk_deep_sleep_khz, clk_mgr_base->clks.dcfclk_deep_sleep_khz)) { in dcn2_update_clocks()
[all …]
H A Ddcn20_clk_mgr.h56 void dcn2_read_clocks_from_hw_dentist(struct clk_mgr *clk_mgr_base);
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/
H A Drv1_clk_mgr.c187 static void rv1_update_clocks(struct clk_mgr *clk_mgr_base, in rv1_update_clocks() argument
191 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); in rv1_update_clocks()
192 struct dc *dc = clk_mgr_base->ctx->dc; in rv1_update_clocks()
224 if (new_clocks->dispclk_khz > clk_mgr_base->clks.dispclk_khz in rv1_update_clocks()
225 || new_clocks->phyclk_khz > clk_mgr_base->clks.phyclk_khz in rv1_update_clocks()
226 || new_clocks->fclk_khz > clk_mgr_base->clks.fclk_khz in rv1_update_clocks()
227 || new_clocks->dcfclk_khz > clk_mgr_base->clks.dcfclk_khz) in rv1_update_clocks()
230 if (should_set_clock(safe_to_lower, new_clocks->phyclk_khz, clk_mgr_base->clks.phyclk_khz)) { in rv1_update_clocks()
231 clk_mgr_base->clks.phyclk_khz = new_clocks->phyclk_khz; in rv1_update_clocks()
239 if (should_set_clock(safe_to_lower, new_clocks->fclk_khz, clk_mgr_base->clks.fclk_khz)) { in rv1_update_clocks()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/
H A Ddce112_clk_mgr.c70 int dce112_set_clock(struct clk_mgr *clk_mgr_base, int requested_clk_khz) in dce112_set_clock() argument
72 struct clk_mgr_internal *clk_mgr_dce = TO_CLK_MGR_INTERNAL(clk_mgr_base); in dce112_set_clock()
74 struct dc_bios *bp = clk_mgr_base->ctx->dc_bios; in dce112_set_clock()
75 struct dc *dc = clk_mgr_base->ctx->dc; in dce112_set_clock()
104 if (!((clk_mgr_base->ctx->asic_id.chip_family == FAMILY_AI) && in dce112_set_clock()
105 ASICREV_IS_VEGA20_P(clk_mgr_base->ctx->asic_id.hw_internal_rev))) in dce112_set_clock()
191 static void dce112_update_clocks(struct clk_mgr *clk_mgr_base, in dce112_update_clocks() argument
195 struct clk_mgr_internal *clk_mgr_dce = TO_CLK_MGR_INTERNAL(clk_mgr_base); in dce112_update_clocks()
203 level_change_req.power_level = dce_get_required_clocks_state(clk_mgr_base, context); in dce112_update_clocks()
207 if (dm_pp_apply_power_level_change_request(clk_mgr_base->ctx, &level_change_req)) in dce112_update_clocks()
[all …]
H A Ddce112_clk_mgr.h35 int dce112_set_clock(struct clk_mgr *clk_mgr_base, int requested_clk_khz);
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dce120/
H A Ddce120_clk_mgr.c84 static void dce12_update_clocks(struct clk_mgr *clk_mgr_base, in dce12_update_clocks() argument
88 struct clk_mgr_internal *clk_mgr_dce = TO_CLK_MGR_INTERNAL(clk_mgr_base); in dce12_update_clocks()
97 if (should_set_clock(safe_to_lower, patched_disp_clk, clk_mgr_base->clks.dispclk_khz)) { in dce12_update_clocks()
107 clk_mgr_base->clks.dispclk_khz = dce112_set_clock(clk_mgr_base, patched_disp_clk); in dce12_update_clocks()
109 dm_pp_apply_clock_for_voltage_request(clk_mgr_base->ctx, &clock_voltage_req); in dce12_update_clocks()
112 if (should_set_clock(safe_to_lower, max_pix_clk, clk_mgr_base->clks.phyclk_khz)) { in dce12_update_clocks()
115 clk_mgr_base->clks.phyclk_khz = max_pix_clk; in dce12_update_clocks()
117 dm_pp_apply_clock_for_voltage_request(clk_mgr_base->ctx, &clock_voltage_req); in dce12_update_clocks()
119 dce11_pplib_apply_display_requirements(clk_mgr_base->ctx->dc, context); in dce12_update_clocks()
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/
H A Ddcn35_clk_mgr.c189 void dcn35_disable_otg_wa(struct clk_mgr *clk_mgr_base, struct dc_state *context, in dcn35_disable_otg_wa() argument
192 struct dc *dc = clk_mgr_base->ctx->dc; in dcn35_disable_otg_wa()
201 struct clk_mgr_internal *clk_mgr_internal = TO_CLK_MGR_INTERNAL(clk_mgr_base); in dcn35_disable_otg_wa()
341 static void dcn35_notify_host_router_bw(struct clk_mgr *clk_mgr_base, struct dc_state *context, in dcn35_notify_host_router_bw() argument
345 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); in dcn35_notify_host_router_bw()
370 …if (should_set_clock(safe_to_lower, new_clocks->host_router_bw_kbps[i], clk_mgr_base->clks.host_ro… in dcn35_notify_host_router_bw()
371 clk_mgr_base->clks.host_router_bw_kbps[i] = new_clocks->host_router_bw_kbps[i]; in dcn35_notify_host_router_bw()
377 void dcn35_update_clocks(struct clk_mgr *clk_mgr_base, in dcn35_update_clocks() argument
382 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); in dcn35_update_clocks()
384 struct dc *dc = clk_mgr_base->ctx->dc; in dcn35_update_clocks()
[all …]
H A Ddcn35_clk_mgr.h52 void dcn35_update_clocks(struct clk_mgr *clk_mgr_base,
68 void dcn35_disable_otg_wa(struct clk_mgr *clk_mgr_base,
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/
H A Ddce_clk_mgr.h34 int dce_get_dp_ref_freq_khz(struct clk_mgr *clk_mgr_base);
36 struct clk_mgr *clk_mgr_base,
51 struct clk_mgr *clk_mgr_base,
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/
H A Dclk_mgr.c386 void dc_destroy_clk_mgr(struct clk_mgr *clk_mgr_base) in dc_destroy_clk_mgr() argument
388 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); in dc_destroy_clk_mgr()
391 switch (clk_mgr_base->ctx->asic_id.chip_family) { in dc_destroy_clk_mgr()
393 if (ASICREV_IS_SIENNA_CICHLID_P(clk_mgr_base->ctx->asic_id.hw_internal_rev)) { in dc_destroy_clk_mgr()
395 } else if (ASICREV_IS_DIMGREY_CAVEFISH_P(clk_mgr_base->ctx->asic_id.hw_internal_rev)) { in dc_destroy_clk_mgr()
398 if (ASICREV_IS_BEIGE_GOBY_P(clk_mgr_base->ctx->asic_id.hw_internal_rev)) { in dc_destroy_clk_mgr()
404 if (ASICREV_IS_VANGOGH(clk_mgr_base->ctx->asic_id.hw_internal_rev)) in dc_destroy_clk_mgr()
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/
H A Ddcn31_clk_mgr.h45 void dcn31_update_clocks(struct clk_mgr *clk_mgr_base,
54 int dcn31_get_dtb_ref_freq_khz(struct clk_mgr *clk_mgr_base);
/linux/drivers/gpu/drm/amd/display/dc/inc/hw/
H A Dclk_mgr.h299 struct clk_mgr *clk_mgr_base, struct clk_log_info *log_info);
336 int (*get_dispclk_from_dentist)(struct clk_mgr *clk_mgr_base);
342 unsigned int (*get_max_clock_khz)(struct clk_mgr *clk_mgr_base, enum clk_type clk_type);