| /linux/drivers/clk/ |
| H A D | clk-versaclock7.c | 886 clk_hw_get_name(hw)); in vc7_fod_recalc_rate()
890 pr_debug("%s - %s: parent_rate: %lu\n", __func__, clk_hw_get_name(hw), parent_rate); in vc7_fod_recalc_rate()
896 __func__, clk_hw_get_name(hw), in vc7_fod_recalc_rate()
898 pr_debug("%s - %s rate: %lu\n", __func__, clk_hw_get_name(hw), fod_rate); in vc7_fod_recalc_rate()
910 __func__, clk_hw_get_name(hw), req->rate, req->best_parent_rate); in vc7_fod_determine_rate()
918 __func__, clk_hw_get_name(hw), in vc7_fod_determine_rate()
920 pr_debug("%s - %s rate: %lu\n", __func__, clk_hw_get_name(hw), fod_rate); in vc7_fod_determine_rate()
934 __func__, clk_hw_get_name(hw), rate, parent_rate); in vc7_fod_set_rate()
939 rate, clk_hw_get_name(hw)); in vc7_fod_set_rate()
949 __func__, clk_hw_get_name(hw), in vc7_fod_set_rate()
[all …]
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| H A D | clk-xgene.c | 65 pr_debug("%s pll %s\n", clk_hw_get_name(hw), in xgene_clk_pll_is_enabled()
113 clk_hw_get_name(hw), fvco / nout, parent_rate, in xgene_clk_pll_recalc_rate()
459 pr_debug("%s clock enabled\n", clk_hw_get_name(hw)); in xgene_clk_enable()
467 clk_hw_get_name(hw), in xgene_clk_enable()
478 clk_hw_get_name(hw), in xgene_clk_enable()
499 pr_debug("%s clock disabled\n", clk_hw_get_name(hw)); in xgene_clk_disable()
525 pr_debug("%s clock checking\n", clk_hw_get_name(hw)); in xgene_clk_is_enabled()
528 pr_debug("%s clock is %s\n", clk_hw_get_name(hw), in xgene_clk_is_enabled()
550 clk_hw_get_name(hw), in xgene_clk_recalc_rate()
556 clk_hw_get_name(hw), parent_rate, parent_rate); in xgene_clk_recalc_rate()
[all …]
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| H A D | clk-fixed-rate_test.c | 188 KUNIT_ASSERT_STREQ(test, parent_name, clk_hw_get_name(parent_hw)); in clk_fixed_rate_parent_test()
221 KUNIT_ASSERT_STREQ(test, parent_name, clk_hw_get_name(parent_hw)); in clk_fixed_rate_parent_rate_test()
251 KUNIT_ASSERT_STREQ(test, parent_name, clk_hw_get_name(parent_hw)); in clk_fixed_rate_parent_accuracy_test()
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| H A D | clk-versaclock5.c | 1068 parent_names[0] = clk_hw_get_name(&vc5->clk_mux); in vc5_probe()
1088 parent_names[0] = clk_hw_get_name(&vc5->clk_mul); in vc5_probe()
1090 parent_names[0] = clk_hw_get_name(&vc5->clk_mux); in vc5_probe()
1108 parent_names[0] = clk_hw_get_name(&vc5->clk_pfd); in vc5_probe()
1131 parent_names[0] = clk_hw_get_name(&vc5->clk_pll.hw); in vc5_probe()
1153 parent_names[0] = clk_hw_get_name(&vc5->clk_mux); in vc5_probe()
1166 parent_names[0] = clk_hw_get_name(&vc5->clk_fod[idx].hw); in vc5_probe()
1168 parent_names[1] = clk_hw_get_name(&vc5->clk_mux); in vc5_probe()
1171 clk_hw_get_name(&vc5->clk_out[n - 1].hw); in vc5_probe()
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| /linux/drivers/clk/ti/ |
| H A D | clockdomain.c | 43 clk_hw_get_name(hw)); in omap2_clkops_enable_clkdm()
49 __func__, clk_hw_get_name(hw)); in omap2_clkops_enable_clkdm()
55 __func__, clk_hw_get_name(hw), clk->clkdm_name, ret); in omap2_clkops_enable_clkdm()
77 clk_hw_get_name(hw)); in omap2_clkops_disable_clkdm()
83 __func__, clk_hw_get_name(hw)); in omap2_clkops_disable_clkdm()
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| H A D | clkt_dflt.c | 106 idlest_val, clk_hw_get_name(&clk->hw)); in _omap2_module_wait_ready()
213 __func__, clk_hw_get_name(hw), in omap2_dflt_clk_enable()
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| H A D | dpll3xxx.c | 69 clk_name = clk_hw_get_name(&clk->hw); in _omap3_wait_dpll_status()
145 pr_debug("clock: locking DPLL %s\n", clk_hw_get_name(&clk->hw)); in _omap3_noncore_dpll_lock()
193 clk_hw_get_name(&clk->hw)); in _omap3_noncore_dpll_bypass()
223 pr_debug("clock: stopping DPLL %s\n", clk_hw_get_name(&clk->hw)); in _omap3_noncore_dpll_stop()
538 __func__, clk_hw_get_name(hw), in omap3_noncore_dpll_enable()
678 clk_hw_get_name(hw), rate); in omap3_noncore_dpll_set_rate()
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| /linux/drivers/clk/ux500/ |
| H A D | clk-prcmu.c | 46 clk_hw_get_name(hw)); in clk_prcmu_unprepare()
79 (char *)clk_hw_get_name(hw), in clk_prcmu_opp_prepare()
83 __func__, clk_hw_get_name(hw)); in clk_prcmu_opp_prepare()
92 (char *)clk_hw_get_name(hw)); in clk_prcmu_opp_prepare()
106 clk_hw_get_name(hw)); in clk_prcmu_opp_unprepare()
112 (char *)clk_hw_get_name(hw)); in clk_prcmu_opp_unprepare()
126 __func__, clk_hw_get_name(hw)); in clk_prcmu_opp_volt_prepare()
148 clk_hw_get_name(hw)); in clk_prcmu_opp_volt_unprepare()
316 clk_hw_get_name(hw)); in clk_prcmu_clkout_unprepare()
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| /linux/drivers/clk/zynqmp/ |
| H A D | pll.c | 53 const char *clk_name = clk_hw_get_name(hw); in zynqmp_pll_get_mode()
76 const char *clk_name = clk_hw_get_name(hw); in zynqmp_pll_set_mode()
138 const char *clk_name = clk_hw_get_name(hw); in zynqmp_pll_recalc_rate()
182 const char *clk_name = clk_hw_get_name(hw); in zynqmp_pll_set_rate()
228 const char *clk_name = clk_hw_get_name(hw); in zynqmp_pll_is_enabled()
252 const char *clk_name = clk_hw_get_name(hw); in zynqmp_pll_enable()
280 const char *clk_name = clk_hw_get_name(hw); in zynqmp_pll_disable()
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| H A D | clk-gate-zynqmp.c | 37 const char *clk_name = clk_hw_get_name(hw); in zynqmp_clk_gate_enable()
57 const char *clk_name = clk_hw_get_name(hw); in zynqmp_clk_gate_disable()
77 const char *clk_name = clk_hw_get_name(hw); in zynqmp_clk_gate_is_enabled()
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| H A D | clk-mux-zynqmp.c | 46 const char *clk_name = clk_hw_get_name(hw); in zynqmp_clk_mux_get_parent()
76 const char *clk_name = clk_hw_get_name(hw); in zynqmp_clk_mux_set_parent()
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| H A D | divider.c | 83 const char *clk_name = clk_hw_get_name(hw); in zynqmp_clk_divider_recalc_rate()
125 const char *clk_name = clk_hw_get_name(hw); in zynqmp_clk_divider_determine_rate()
176 const char *clk_name = clk_hw_get_name(hw); in zynqmp_clk_divider_set_rate()
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| /linux/drivers/clk/sunxi-ng/ |
| H A D | ccu_frac.c | 71 pr_debug("%s: Read fractional\n", clk_hw_get_name(&common->hw)); in ccu_frac_helper_read_rate()
77 clk_hw_get_name(&common->hw), cf->rates[0], cf->rates[1]); in ccu_frac_helper_read_rate()
82 clk_hw_get_name(&common->hw), reg, cf->select); in ccu_frac_helper_read_rate()
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| H A D | ccu_sdm.c | 118 clk_hw_get_name(&common->hw)); in ccu_sdm_helper_read_rate()
124 clk_hw_get_name(&common->hw)); in ccu_sdm_helper_read_rate()
129 clk_hw_get_name(&common->hw), reg); in ccu_sdm_helper_read_rate()
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| /linux/drivers/clk/qcom/ |
| H A D | clk-regmap-mux-div.c | 27 const char *name = clk_hw_get_name(&md->clkr.hw); in mux_div_set_src_div()
63 const char *name = clk_hw_get_name(&md->clkr.hw); in mux_div_get_src_div()
166 const char *name = clk_hw_get_name(hw); in mux_div_get_parent()
208 const char *name = clk_hw_get_name(hw); in mux_div_recalc_rate()
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| H A D | clk-branch.c | 66 const char *name = clk_hw_get_name(&br->clkr.hw); in clk_branch_wait()
151 WARN(1, "%s mem enable failed\n", clk_hw_get_name(&branch.clkr.hw)); in clk_branch2_mem_enable()
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| /linux/drivers/clk/bcm/ |
| H A D | clk-raspberrypi.c | 220 clk_hw_get_name(hw), ret); in raspberrypi_fw_is_prepared()
240 clk_hw_get_name(hw), ret); in raspberrypi_fw_get_rate()
259 clk_hw_get_name(hw), ret); in raspberrypi_fw_set_rate()
301 clk_hw_get_name(hw), ret); in raspberrypi_fw_prepare()
318 clk_hw_get_name(hw), ret); in raspberrypi_fw_unprepare()
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| /linux/drivers/clk/berlin/ |
| H A D | berlin2-pll.c | 53 pr_warn("%s has zero rfdiv\n", clk_hw_get_name(hw)); in berlin2_pll_recalc_rate()
62 clk_hw_get_name(hw), vcodivsel); in berlin2_pll_recalc_rate()
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| /linux/drivers/clk/st/ |
| H A D | clkgen-fsyn.c | 342 clk_hw_get_name(hw), __func__); in quadfs_pll_fs660c32_recalc_rate()
389 __func__, clk_hw_get_name(hw), in quadfs_pll_fs660c32_determine_rate()
414 __func__, clk_hw_get_name(hw), in quadfs_pll_fs660c32_set_rate()
572 pr_debug("%s: %s\n", __func__, clk_hw_get_name(hw)); in quadfs_fsynth_enable()
597 pr_debug("%s: %s\n", __func__, clk_hw_get_name(hw)); in quadfs_fsynth_disable()
614 __func__, clk_hw_get_name(hw), nsb); in quadfs_fsynth_is_enabled()
808 clk_hw_get_name(hw), __func__); in quadfs_recalc_rate()
811 pr_debug("%s:%s rate %lu\n", clk_hw_get_name(hw), __func__, rate); in quadfs_recalc_rate()
825 __func__, clk_hw_get_name(hw), in quadfs_determine_rate()
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| /linux/drivers/clk/imx/ |
| H A D | clk-lpcg-scu.c | 164 if (!strncmp("hdmi_lpcg", clk_hw_get_name(&clk->hw), strlen("hdmi_lpcg"))) in imx_clk_lpcg_scu_suspend()
177 if (!strncmp("hdmi_lpcg", clk_hw_get_name(&clk->hw), strlen("hdmi_lpcg"))) in imx_clk_lpcg_scu_resume()
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| /linux/drivers/clk/samsung/ |
| H A D | clk-pll.c | 95 pr_err("Could not lock PLL %s\n", clk_hw_get_name(&pll->hw)); in samsung_pll_lock_wait()
244 drate, clk_hw_get_name(hw)); in samsung_pll35xx_set_rate()
357 drate, clk_hw_get_name(hw)); in samsung_pll36xx_set_rate()
472 drate, clk_hw_get_name(hw)); in samsung_pll0822x_set_rate()
561 drate, clk_hw_get_name(hw)); in samsung_pll0831x_set_rate()
671 drate, clk_hw_get_name(hw)); in samsung_pll45xx_set_rate()
808 drate, clk_hw_get_name(hw)); in samsung_pll46xx_set_rate()
1046 drate, clk_hw_get_name(hw)); in samsung_pll2550xx_set_rate()
1141 drate, clk_hw_get_name(hw)); in samsung_pll2650x_set_rate()
1231 drate, clk_hw_get_name(hw)); in samsung_pll2650xx_set_rate()
[all …]
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| /linux/drivers/clk/socfpga/ |
| H A D | clk-gate.c | 33 const char *name = clk_hw_get_name(hwclk); in socfpga_clk_get_parent()
59 const char *name = clk_hw_get_name(hwclk); in socfpga_clk_set_parent()
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| /linux/drivers/clk/sophgo/ |
| H A D | clk-sg2042-pll.c | 345 clk_hw_get_name(hw), rate); in sg2042_clk_pll_recalc_rate()
370 clk_hw_get_name(hw), proper_rate); in sg2042_clk_pll_determine_rate()
407 clk_hw_get_name(hw), value); in sg2042_clk_pll_set_rate()
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| /linux/include/trace/events/ |
| H A D | clk.h | 275 __string( pname, req->best_parent_hw ? clk_hw_get_name(req->best_parent_hw) : "none" )
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| /linux/drivers/clk/nxp/ |
| H A D | clk-lpc32xx.c | 516 clk_hw_get_name(hw), in clk_pll_recalc_rate()
525 clk_hw_get_name(hw), in clk_pll_recalc_rate()
589 pr_debug("%s: %lu/%lu\n", clk_hw_get_name(hw), req->best_parent_rate, req->rate); in clk_hclk_pll_determine_rate()
618 clk_hw_get_name(hw), req->rate); in clk_hclk_pll_determine_rate()
636 clk_hw_get_name(hw), req->rate, m, n, p); in clk_hclk_pll_determine_rate()
639 clk_hw_get_name(hw), req->rate, m, n, p, o); in clk_hclk_pll_determine_rate()
653 pr_debug("%s: %lu/%lu\n", clk_hw_get_name(hw), req->best_parent_rate, in clk_usb_pll_determine_rate()
804 pr_debug("%s: 0x%x\n", clk_hw_get_name(hw), clk->enable); in clk_usb_enable()
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