Searched refs:clk_hw_get_flags (Results 1 – 24 of 24) sorted by relevance
75 if (!(clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT)) { in __bestmult()
312 if (!(clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT)) { in clk_divider_bestdiv()385 if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) { in divider_ro_determine_rate()
38 if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) { in clk_factor_determine_rate()
23 KUNIT_EXPECT_EQ(test, 0UL, clk_hw_get_flags(ret)); in clk_gate_register_test_dev()
74 if (clk_hw_get_flags(hw) & CLK_SET_RATE_NO_REPARENT) { in clk_composite_determine_rate()
310 if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) { in cdce706_divider_determine_rate()
673 if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) { in si5351_msynth_determine_rate()1062 if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) { in si5351_clkout_determine_rate()
852 if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) { in si5341_output_clk_determine_rate()
455 if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) { in clk_apb_mul_determine_rate()
644 unsigned long clk_hw_get_flags(const struct clk_hw *hw) in clk_hw_get_flags() function648 EXPORT_SYMBOL_GPL(clk_hw_get_flags);
1107 if ((clk_hw_get_flags(hw) & CLK_SET_RATE_NO_REPARENT)) { in rp1_clock_determine_rate()
78 if (!(clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT)) { in owl_clk_val_best()
124 if (clk_hw_get_flags(clk) & CLK_SET_RATE_PARENT) in sun9i_a80_cpus_clk_determine_rate()
106 if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) in clk_factors_determine_rate()
48 if (!(clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT)) { in clk_half_divider_bestdiv()
157 if (divider->is_frac && (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) && in zynqmp_clk_divider_determine_rate()
91 if (clk_hw_get_flags(hw) & CLK_SET_RATE_NO_REPARENT) { in ccu_mux_helper_determine_rate()
181 if (!(clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT)) { in ti_clk_divider_bestdiv()
130 if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) { in flexgen_determine_rate()
1489 unsigned long clk_hw_get_flags(const struct clk_hw *hw);1491 (clk_hw_get_flags((hw)) & CLK_SET_RATE_PARENT)
1424 if (clk_hw_get_flags(&clk->hw) & CLK_IS_CRITICAL) in rzg2l_mod_clock_module_set_state()1429 clk_hw_get_flags(&clock->hw) & CLK_IS_CRITICAL) in rzg2l_mod_clock_module_set_state()1672 if ((clk_hw_get_flags(&clk->hw) & CLK_IS_CRITICAL) && in rzg2l_mod_enable_crit_clock_init_mstop()
145 if (!(clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT)) { in davinci_pll_determine_rate()
256 clk_flags = clk_hw_get_flags(hw); in _freq_tbl_determine_rate()363 clk_flags = clk_hw_get_flags(hw); in _freq_tbl_fm_determine_rate()
415 clk_flags = clk_hw_get_flags(hw); in _freq_tbl_determine_rate()