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Searched refs:clk_ctrl (Results 1 – 15 of 15) sorted by relevance

/linux/arch/mips/ath79/
H A Dclock.c238 u32 pll, out_div, ref_div, nint, nfrac, frac, clk_ctrl, postdiv; in ar934x_clocks_init() local
307 clk_ctrl = __raw_readl(pll_base + AR934X_PLL_CPU_DDR_CLK_CTRL_REG); in ar934x_clocks_init()
309 postdiv = (clk_ctrl >> AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_SHIFT) & in ar934x_clocks_init()
312 if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_PLL_BYPASS) in ar934x_clocks_init()
314 else if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_CPUCLK_FROM_CPUPLL) in ar934x_clocks_init()
319 postdiv = (clk_ctrl >> AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_SHIFT) & in ar934x_clocks_init()
322 if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_PLL_BYPASS) in ar934x_clocks_init()
324 else if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_DDRCLK_FROM_DDRPLL) in ar934x_clocks_init()
329 postdiv = (clk_ctrl >> AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_SHIFT) & in ar934x_clocks_init()
332 if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_PLL_BYPASS) in ar934x_clocks_init()
[all …]
/linux/drivers/clk/aspeed/
H A Dclk-ast2700.c623 struct ast2700_clk_ctrl *clk_ctrl) in ast2700_clk_hw_register_fixed_display() argument
629 val = readl(clk_ctrl->base + SCU0_CLK_SEL2); in ast2700_clk_hw_register_fixed_display()
641 return devm_clk_hw_register_fixed_rate(clk_ctrl->dev, name, NULL, 0, (xdclk * mult) / div); in ast2700_clk_hw_register_fixed_display()
646 struct ast2700_clk_ctrl *clk_ctrl) in ast2700_clk_hw_register_hpll() argument
651 val = readl(clk_ctrl->base + SCU0_HWSTRAP1); in ast2700_clk_hw_register_hpll()
652 if ((readl(clk_ctrl->base) & REVISION_ID) && (val & BIT(3))) { in ast2700_clk_hw_register_hpll()
655 return devm_clk_hw_register_fixed_rate(clk_ctrl->dev, name, NULL, in ast2700_clk_hw_register_hpll()
658 return devm_clk_hw_register_fixed_rate(clk_ctrl->dev, name, NULL, in ast2700_clk_hw_register_hpll()
661 return devm_clk_hw_register_fixed_rate(clk_ctrl->dev, name, NULL, in ast2700_clk_hw_register_hpll()
664 return devm_clk_hw_register_fixed_rate(clk_ctrl->dev, name, NULL, in ast2700_clk_hw_register_hpll()
[all …]
/linux/drivers/gpu/drm/msm/disp/dpu1/catalog/
H A Ddpu_8_1_sm8450.h74 .clk_ctrl = DPU_CLK_CTRL_VIG0,
82 .clk_ctrl = DPU_CLK_CTRL_VIG1,
90 .clk_ctrl = DPU_CLK_CTRL_VIG2,
98 .clk_ctrl = DPU_CLK_CTRL_VIG3,
106 .clk_ctrl = DPU_CLK_CTRL_DMA0,
114 .clk_ctrl = DPU_CLK_CTRL_DMA1,
122 .clk_ctrl = DPU_CLK_CTRL_DMA2,
130 .clk_ctrl = DPU_CLK_CTRL_DMA3,
304 .clk_ctrl = DPU_CLK_CTRL_WB2,
H A Ddpu_8_4_sa8775p.h73 .clk_ctrl = DPU_CLK_CTRL_VIG0,
81 .clk_ctrl = DPU_CLK_CTRL_VIG1,
89 .clk_ctrl = DPU_CLK_CTRL_VIG2,
97 .clk_ctrl = DPU_CLK_CTRL_VIG3,
105 .clk_ctrl = DPU_CLK_CTRL_DMA0,
113 .clk_ctrl = DPU_CLK_CTRL_DMA1,
121 .clk_ctrl = DPU_CLK_CTRL_DMA2,
129 .clk_ctrl = DPU_CLK_CTRL_DMA3,
311 .clk_ctrl = DPU_CLK_CTRL_WB2,
H A Ddpu_8_0_sc8280xp.h73 .clk_ctrl = DPU_CLK_CTRL_VIG0,
81 .clk_ctrl = DPU_CLK_CTRL_VIG1,
89 .clk_ctrl = DPU_CLK_CTRL_VIG2,
97 .clk_ctrl = DPU_CLK_CTRL_VIG3,
105 .clk_ctrl = DPU_CLK_CTRL_DMA0,
113 .clk_ctrl = DPU_CLK_CTRL_DMA1,
121 .clk_ctrl = DPU_CLK_CTRL_DMA2,
129 .clk_ctrl = DPU_CLK_CTRL_DMA3,
/linux/include/linux/platform_data/
H A Dnet-cw1200.h19 int (*clk_ctrl)(const struct cw1200_platform_data_spi *pdata, member
34 int (*clk_ctrl)(const struct cw1200_platform_data_sdio *pdata, member
/linux/drivers/net/wireless/st/cw1200/
H A Dcw1200_sdio.c194 if (pdata->clk_ctrl) in cw1200_sdio_off()
195 pdata->clk_ctrl(pdata, false); in cw1200_sdio_off()
228 if (pdata->clk_ctrl) { in cw1200_sdio_on()
229 if (pdata->clk_ctrl(pdata, true)) { in cw1200_sdio_on()
H A Dcw1200_spi.c290 if (pdata->clk_ctrl) in cw1200_spi_off()
291 pdata->clk_ctrl(pdata, false); in cw1200_spi_off()
313 if (pdata->clk_ctrl) { in cw1200_spi_on()
314 if (pdata->clk_ctrl(pdata, true)) { in cw1200_spi_on()
/linux/drivers/clk/zynq/
H A Dclkc.c176 const char *clk_name1, void __iomem *clk_ctrl, in zynq_clk_register_periph_clk() argument
192 CLK_SET_RATE_NO_REPARENT, clk_ctrl, 4, 2, 0, lock); in zynq_clk_register_periph_clk()
194 clk_register_divider(NULL, div_name, mux_name, 0, clk_ctrl, 8, 6, in zynq_clk_register_periph_clk()
198 CLK_SET_RATE_PARENT, clk_ctrl, 0, 0, lock); in zynq_clk_register_periph_clk()
201 CLK_SET_RATE_PARENT, clk_ctrl, 1, 0, lock); in zynq_clk_register_periph_clk()
/linux/drivers/gpu/drm/msm/disp/dpu1/
H A Ddpu_hw_catalog.h428 enum dpu_clk_ctrl_type clk_ctrl; member
544 enum dpu_clk_ctrl_type clk_ctrl; member
H A Ddpu_hw_top.h108 enum dpu_clk_ctrl_type clk_ctrl, bool enable);
H A Ddpu_encoder_phys_wb.c48 *forced_on = mdp->ops.setup_clk_force_ctrl(mdp, wb->caps->clk_ctrl, enable); in _dpu_encoder_phys_wb_clk_force_ctrl()
H A Ddpu_plane.c346 *forced_on = mdp->ops.setup_clk_force_ctrl(mdp, sspp->cap->clk_ctrl, enable); in _dpu_plane_sspp_clk_force_ctrl()
/linux/drivers/clk/bcm/
H A Dclk-iproc.h207 const struct iproc_clk_ctrl *clk_ctrl,
H A Dclk-iproc-pll.c719 const struct iproc_clk_ctrl *clk_ctrl, in iproc_pll_clk_setup() argument
731 if (WARN_ON(!pll_ctrl) || WARN_ON(!clk_ctrl)) in iproc_pll_clk_setup()
815 iclk->ctrl = &clk_ctrl[i]; in iproc_pll_clk_setup()