1perf-intel-pt(1) 2================ 3 4NAME 5---- 6perf-intel-pt - Support for Intel Processor Trace within perf tools 7 8SYNOPSIS 9-------- 10[verse] 11'perf record' -e intel_pt// 12 13DESCRIPTION 14----------- 15 16Intel Processor Trace (Intel PT) is an extension of Intel Architecture that 17collects information about software execution such as control flow, execution 18modes and timings and formats it into highly compressed binary packets. 19Technical details are documented in the Intel 64 and IA-32 Architectures 20Software Developer Manuals, Chapter 36 Intel Processor Trace. 21 22Intel PT is first supported in Intel Core M and 5th generation Intel Core 23processors that are based on the Intel micro-architecture code name Broadwell. 24 25Trace data is collected by 'perf record' and stored within the perf.data file. 26See below for options to 'perf record'. 27 28Trace data must be 'decoded' which involves walking the object code and matching 29the trace data packets. For example a TNT packet only tells whether a 30conditional branch was taken or not taken, so to make use of that packet the 31decoder must know precisely which instruction was being executed. 32 33Decoding is done on-the-fly. The decoder outputs samples in the same format as 34samples output by perf hardware events, for example as though the "instructions" 35or "branches" events had been recorded. Presently 3 tools support this: 36'perf script', 'perf report' and 'perf inject'. See below for more information 37on using those tools. 38 39The main distinguishing feature of Intel PT is that the decoder can determine 40the exact flow of software execution. Intel PT can be used to understand why 41and how did software get to a certain point, or behave a certain way. The 42software does not have to be recompiled, so Intel PT works with debug or release 43builds, however the executed images are needed - which makes use in JIT-compiled 44environments, or with self-modified code, a challenge. Also symbols need to be 45provided to make sense of addresses. 46 47A limitation of Intel PT is that it produces huge amounts of trace data 48(hundreds of megabytes per second per core) which takes a long time to decode, 49for example two or three orders of magnitude longer than it took to collect. 50Another limitation is the performance impact of tracing, something that will 51vary depending on the use-case and architecture. 52 53 54Quickstart 55---------- 56 57It is important to start small. That is because it is easy to capture vastly 58more data than can possibly be processed. 59 60The simplest thing to do with Intel PT is userspace profiling of small programs. 61Data is captured with 'perf record' e.g. to trace 'ls' userspace-only: 62 63 perf record -e intel_pt//u ls 64 65And profiled with 'perf report' e.g. 66 67 perf report 68 69To also trace kernel space presents a problem, namely kernel self-modifying 70code. A fairly good kernel image is available in /proc/kcore but to get an 71accurate image a copy of /proc/kcore needs to be made under the same conditions 72as the data capture. 'perf record' can make a copy of /proc/kcore if the option 73--kcore is used, but access to /proc/kcore is restricted e.g. 74 75 sudo perf record -o pt_ls --kcore -e intel_pt// -- ls 76 77which will create a directory named 'pt_ls' and put the perf.data file (named 78simply 'data') and copies of /proc/kcore, /proc/kallsyms and /proc/modules into 79it. The other tools understand the directory format, so to use 'perf report' 80becomes: 81 82 sudo perf report -i pt_ls 83 84Because samples are synthesized after-the-fact, the sampling period can be 85selected for reporting. e.g. sample every microsecond 86 87 sudo perf report pt_ls --itrace=i1usge 88 89See the sections below for more information about the --itrace option. 90 91Beware the smaller the period, the more samples that are produced, and the 92longer it takes to process them. 93 94Also note that the coarseness of Intel PT timing information will start to 95distort the statistical value of the sampling as the sampling period becomes 96smaller. 97 98To represent software control flow, "branches" samples are produced. By default 99a branch sample is synthesized for every single branch. To get an idea what 100data is available you can use the 'perf script' tool with all itrace sampling 101options, which will list all the samples. 102 103 perf record -e intel_pt//u ls 104 perf script --itrace=iybxwpe 105 106An interesting field that is not printed by default is 'flags' which can be 107displayed as follows: 108 109 perf script --itrace=iybxwpe -F+flags 110 111The flags are "bcrosyiABExghDt" which stand for branch, call, return, conditional, 112system, asynchronous, interrupt, transaction abort, trace begin, trace end, 113in transaction, VM-entry, VM-exit, interrupt disabled, and interrupt disable 114toggle respectively. 115 116perf script also supports higher level ways to dump instruction traces: 117 118 perf script --insn-trace=disasm 119 120or to use the xed disassembler, which requires installing the xed tool 121(see XED below): 122 123 perf script --insn-trace --xed 124 125Dumping all instructions in a long trace can be fairly slow. It is usually better 126to start with higher level decoding, like 127 128 perf script --call-trace 129 130or 131 132 perf script --call-ret-trace 133 134and then select a time range of interest. The time range can then be examined 135in detail with 136 137 perf script --time starttime,stoptime --insn-trace=disasm 138 139While examining the trace it's also useful to filter on specific CPUs using 140the -C option 141 142 perf script --time starttime,stoptime --insn-trace=disasm -C 1 143 144Dump all instructions in time range on CPU 1. 145 146Another interesting field that is not printed by default is 'ipc' which can be 147displayed as follows: 148 149 perf script --itrace=be -F+ipc 150 151There are two ways that instructions-per-cycle (IPC) can be calculated depending 152on the recording. 153 154If the 'cyc' config term (see config terms section below) was used, then IPC 155and cycle events are calculated using the cycle count from CYC packets, otherwise 156MTC packets are used - refer to the 'mtc' config term. When MTC is used, however, 157the values are less accurate because the timing is less accurate. 158 159Because Intel PT does not update the cycle count on every branch or instruction, 160the values will often be zero. When there are values, they will be the number 161of instructions and number of cycles since the last update, and thus represent 162the average IPC cycle count since the last IPC for that event type. 163Note IPC for "branches" events is calculated separately from IPC for "instructions" 164events. 165 166Even with the 'cyc' config term, it is possible to produce IPC information for 167every change of timestamp, but at the expense of accuracy. That is selected by 168specifying the itrace 'A' option. Due to the granularity of timestamps, the 169actual number of cycles increases even though the cycles reported does not. 170The number of instructions is known, but if IPC is reported, cycles can be too 171low and so IPC is too high. Note that inaccuracy decreases as the period of 172sampling increases i.e. if the number of cycles is too low by a small amount, 173that becomes less significant if the number of cycles is large. It may also be 174useful to use the 'A' option in conjunction with dlfilter-show-cycles.so to 175provide higher granularity cycle information. 176 177Also note that the IPC instruction count may or may not include the current 178instruction. If the cycle count is associated with an asynchronous branch 179(e.g. page fault or interrupt), then the instruction count does not include the 180current instruction, otherwise it does. That is consistent with whether or not 181that instruction has retired when the cycle count is updated. 182 183Another note, in the case of "branches" events, non-taken branches are not 184presently sampled, so IPC values for them do not appear e.g. a CYC packet with a 185TNT packet that starts with a non-taken branch. To see every possible IPC 186value, "instructions" events can be used e.g. --itrace=i0ns 187 188While it is possible to create scripts to analyze the data, an alternative 189approach is available to export the data to a sqlite or postgresql database. 190Refer to script export-to-sqlite.py or export-to-postgresql.py for more details, 191and to script exported-sql-viewer.py for an example of using the database. 192 193There is also script intel-pt-events.py which provides an example of how to 194unpack the raw data for power events and PTWRITE. The script also displays 195branches, and supports 2 additional modes selected by option: 196 197 - --insn-trace - instruction trace 198 - --src-trace - source trace 199 200The intel-pt-events.py script also has options: 201 202 - --all-switch-events - display all switch events, not only the last consecutive. 203 - --interleave [<n>] - interleave sample output for the same timestamp so that 204 no more than n samples for a CPU are displayed in a row. 'n' defaults to 4. 205 Note this only affects the order of output, and only when the timestamp is the 206 same. 207 208As mentioned above, it is easy to capture too much data. One way to limit the 209data captured is to use 'snapshot' mode which is explained further below. 210Refer to 'new snapshot option' and 'Intel PT modes of operation' further below. 211 212Another problem that will be experienced is decoder errors. They can be caused 213by inability to access the executed image, self-modified or JIT-ed code, or the 214inability to match side-band information (such as context switches and mmaps) 215which results in the decoder not knowing what code was executed. 216 217There is also the problem of perf not being able to copy the data fast enough, 218resulting in data lost because the buffer was full. See 'Buffer handling' below 219for more details. 220 221 222perf record 223----------- 224 225new event 226~~~~~~~~~ 227 228The Intel PT kernel driver creates a new PMU for Intel PT. PMU events are 229selected by providing the PMU name followed by the "config" separated by slashes. 230An enhancement has been made to allow default "config" e.g. the option 231 232 -e intel_pt// 233 234will use a default config value. Currently that is the same as 235 236 -e intel_pt/tsc,noretcomp=0/ 237 238which is the same as 239 240 -e intel_pt/tsc=1,noretcomp=0/ 241 242Note there are now new config terms - see section 'config terms' further below. 243 244The config terms are listed in /sys/devices/intel_pt/format. They are bit 245fields within the config member of the struct perf_event_attr which is 246passed to the kernel by the perf_event_open system call. They correspond to bit 247fields in the IA32_RTIT_CTL MSR. Here is a list of them and their definitions: 248 249 $ grep -H . /sys/bus/event_source/devices/intel_pt/format/* 250 /sys/bus/event_source/devices/intel_pt/format/cyc:config:1 251 /sys/bus/event_source/devices/intel_pt/format/cyc_thresh:config:19-22 252 /sys/bus/event_source/devices/intel_pt/format/mtc:config:9 253 /sys/bus/event_source/devices/intel_pt/format/mtc_period:config:14-17 254 /sys/bus/event_source/devices/intel_pt/format/noretcomp:config:11 255 /sys/bus/event_source/devices/intel_pt/format/psb_period:config:24-27 256 /sys/bus/event_source/devices/intel_pt/format/tsc:config:10 257 258Note that the default config must be overridden for each term i.e. 259 260 -e intel_pt/noretcomp=0/ 261 262is the same as: 263 264 -e intel_pt/tsc=1,noretcomp=0/ 265 266So, to disable TSC packets use: 267 268 -e intel_pt/tsc=0/ 269 270It is also possible to specify the config value explicitly: 271 272 -e intel_pt/config=0x400/ 273 274Note that, as with all events, the event is suffixed with event modifiers: 275 276 u userspace 277 k kernel 278 h hypervisor 279 G guest 280 H host 281 p precise ip 282 283'h', 'G' and 'H' are for virtualization which are not used by Intel PT. 284'p' is also not relevant to Intel PT. So only options 'u' and 'k' are 285meaningful for Intel PT. 286 287perf_event_attr is displayed if the -vv option is used e.g. 288 289 ------------------------------------------------------------ 290 perf_event_attr: 291 type 6 292 size 112 293 config 0x400 294 { sample_period, sample_freq } 1 295 sample_type IP|TID|TIME|CPU|IDENTIFIER 296 read_format ID 297 disabled 1 298 inherit 1 299 exclude_kernel 1 300 exclude_hv 1 301 enable_on_exec 1 302 sample_id_all 1 303 ------------------------------------------------------------ 304 sys_perf_event_open: pid 31104 cpu 0 group_fd -1 flags 0x8 305 sys_perf_event_open: pid 31104 cpu 1 group_fd -1 flags 0x8 306 sys_perf_event_open: pid 31104 cpu 2 group_fd -1 flags 0x8 307 sys_perf_event_open: pid 31104 cpu 3 group_fd -1 flags 0x8 308 ------------------------------------------------------------ 309 310 311config terms 312~~~~~~~~~~~~ 313 314The June 2015 version of Intel 64 and IA-32 Architectures Software Developer 315Manuals, Chapter 36 Intel Processor Trace, defined new Intel PT features. 316Some of the features are reflect in new config terms. All the config terms are 317described below. 318 319tsc Always supported. Produces TSC timestamp packets to provide 320 timing information. In some cases it is possible to decode 321 without timing information, for example a per-thread context 322 that does not overlap executable memory maps. 323 324 The default config selects tsc (i.e. tsc=1). 325 326noretcomp Always supported. Disables "return compression" so a TIP packet 327 is produced when a function returns. Causes more packets to be 328 produced but might make decoding more reliable. 329 330 The default config does not select noretcomp (i.e. noretcomp=0). 331 332psb_period Allows the frequency of PSB packets to be specified. 333 334 The PSB packet is a synchronization packet that provides a 335 starting point for decoding or recovery from errors. 336 337 Support for psb_period is indicated by: 338 339 /sys/bus/event_source/devices/intel_pt/caps/psb_cyc 340 341 which contains "1" if the feature is supported and "0" 342 otherwise. 343 344 Valid values are given by: 345 346 /sys/bus/event_source/devices/intel_pt/caps/psb_periods 347 348 which contains a hexadecimal value, the bits of which represent 349 valid values e.g. bit 2 set means value 2 is valid. 350 351 The psb_period value is converted to the approximate number of 352 trace bytes between PSB packets as: 353 354 2 ^ (value + 11) 355 356 e.g. value 3 means 16KiB bytes between PSBs 357 358 If an invalid value is entered, the error message 359 will give a list of valid values e.g. 360 361 $ perf record -e intel_pt/psb_period=15/u uname 362 Invalid psb_period for intel_pt. Valid values are: 0-5 363 364 If MTC packets are selected, the default config selects a value 365 of 3 (i.e. psb_period=3) or the nearest lower value that is 366 supported (0 is always supported). Otherwise the default is 0. 367 368 If decoding is expected to be reliable and the buffer is large 369 then a large PSB period can be used. 370 371 Because a TSC packet is produced with PSB, the PSB period can 372 also affect the granularity to timing information in the absence 373 of MTC or CYC. 374 375mtc Produces MTC timing packets. 376 377 MTC packets provide finer grain timestamp information than TSC 378 packets. MTC packets record time using the hardware crystal 379 clock (CTC) which is related to TSC packets using a TMA packet. 380 381 Support for this feature is indicated by: 382 383 /sys/bus/event_source/devices/intel_pt/caps/mtc 384 385 which contains "1" if the feature is supported and 386 "0" otherwise. 387 388 The frequency of MTC packets can also be specified - see 389 mtc_period below. 390 391mtc_period Specifies how frequently MTC packets are produced - see mtc 392 above for how to determine if MTC packets are supported. 393 394 Valid values are given by: 395 396 /sys/bus/event_source/devices/intel_pt/caps/mtc_periods 397 398 which contains a hexadecimal value, the bits of which represent 399 valid values e.g. bit 2 set means value 2 is valid. 400 401 The mtc_period value is converted to the MTC frequency as: 402 403 CTC-frequency / (2 ^ value) 404 405 e.g. value 3 means one eighth of CTC-frequency 406 407 Where CTC is the hardware crystal clock, the frequency of which 408 can be related to TSC via values provided in cpuid leaf 0x15. 409 410 If an invalid value is entered, the error message 411 will give a list of valid values e.g. 412 413 $ perf record -e intel_pt/mtc_period=15/u uname 414 Invalid mtc_period for intel_pt. Valid values are: 0,3,6,9 415 416 The default value is 3 or the nearest lower value 417 that is supported (0 is always supported). 418 419cyc Produces CYC timing packets. 420 421 CYC packets provide even finer grain timestamp information than 422 MTC and TSC packets. A CYC packet contains the number of CPU 423 cycles since the last CYC packet. Unlike MTC and TSC packets, 424 CYC packets are only sent when another packet is also sent. 425 426 Support for this feature is indicated by: 427 428 /sys/bus/event_source/devices/intel_pt/caps/psb_cyc 429 430 which contains "1" if the feature is supported and 431 "0" otherwise. 432 433 The number of CYC packets produced can be reduced by specifying 434 a threshold - see cyc_thresh below. 435 436cyc_thresh Specifies how frequently CYC packets are produced - see cyc 437 above for how to determine if CYC packets are supported. 438 439 Valid cyc_thresh values are given by: 440 441 /sys/bus/event_source/devices/intel_pt/caps/cycle_thresholds 442 443 which contains a hexadecimal value, the bits of which represent 444 valid values e.g. bit 2 set means value 2 is valid. 445 446 The cyc_thresh value represents the minimum number of CPU cycles 447 that must have passed before a CYC packet can be sent. The 448 number of CPU cycles is: 449 450 2 ^ (value - 1) 451 452 e.g. value 4 means 8 CPU cycles must pass before a CYC packet 453 can be sent. Note a CYC packet is still only sent when another 454 packet is sent, not at, e.g. every 8 CPU cycles. 455 456 If an invalid value is entered, the error message 457 will give a list of valid values e.g. 458 459 $ perf record -e intel_pt/cyc,cyc_thresh=15/u uname 460 Invalid cyc_thresh for intel_pt. Valid values are: 0-12 461 462 CYC packets are not requested by default. 463 464pt Specifies pass-through which enables the 'branch' config term. 465 466 The default config selects 'pt' if it is available, so a user will 467 never need to specify this term. 468 469branch Enable branch tracing. Branch tracing is enabled by default so to 470 disable branch tracing use 'branch=0'. 471 472 The default config selects 'branch' if it is available. 473 474ptw Enable PTWRITE packets which are produced when a ptwrite instruction 475 is executed. 476 477 Support for this feature is indicated by: 478 479 /sys/bus/event_source/devices/intel_pt/caps/ptwrite 480 481 which contains "1" if the feature is supported and 482 "0" otherwise. 483 484 As an alternative, refer to "Emulated PTWRITE" further below. 485 486fup_on_ptw Enable a FUP packet to follow the PTWRITE packet. The FUP packet 487 provides the address of the ptwrite instruction. In the absence of 488 fup_on_ptw, the decoder will use the address of the previous branch 489 if branch tracing is enabled, otherwise the address will be zero. 490 Note that fup_on_ptw will work even when branch tracing is disabled. 491 492pwr_evt Enable power events. The power events provide information about 493 changes to the CPU C-state. 494 495 Support for this feature is indicated by: 496 497 /sys/bus/event_source/devices/intel_pt/caps/power_event_trace 498 499 which contains "1" if the feature is supported and 500 "0" otherwise. 501 502event Enable Event Trace. The events provide information about asynchronous 503 events. 504 505 Support for this feature is indicated by: 506 507 /sys/bus/event_source/devices/intel_pt/caps/event_trace 508 509 which contains "1" if the feature is supported and 510 "0" otherwise. 511 512notnt Disable TNT packets. Without TNT packets, it is not possible to walk 513 executable code to reconstruct control flow, however FUP, TIP, TIP.PGE 514 and TIP.PGD packets still indicate asynchronous control flow, and (if 515 return compression is disabled - see noretcomp) return statements. 516 The advantage of eliminating TNT packets is reducing the size of the 517 trace and corresponding tracing overhead. 518 519 Support for this feature is indicated by: 520 521 /sys/bus/event_source/devices/intel_pt/caps/tnt_disable 522 523 which contains "1" if the feature is supported and 524 "0" otherwise. 525 526 527AUX area sampling option 528~~~~~~~~~~~~~~~~~~~~~~~~ 529 530To select Intel PT "sampling" the AUX area sampling option can be used: 531 532 --aux-sample 533 534Optionally it can be followed by the sample size in bytes e.g. 535 536 --aux-sample=8192 537 538In addition, the Intel PT event to sample must be defined e.g. 539 540 -e intel_pt//u 541 542Samples on other events will be created containing Intel PT data e.g. the 543following will create Intel PT samples on the branch-misses event, note the 544events must be grouped using {}: 545 546 perf record --aux-sample -e '{intel_pt//u,branch-misses:u}' 547 548An alternative to '--aux-sample' is to add the config term 'aux-sample-size' to 549events. In this case, the grouping is implied e.g. 550 551 perf record -e intel_pt//u -e branch-misses/aux-sample-size=8192/u 552 553is the same as: 554 555 perf record -e '{intel_pt//u,branch-misses/aux-sample-size=8192/u}' 556 557but allows for also using an address filter e.g.: 558 559 perf record -e intel_pt//u --filter 'filter * @/bin/ls' -e branch-misses/aux-sample-size=8192/u -- ls 560 561It is important to select a sample size that is big enough to contain at least 562one PSB packet. If not a warning will be displayed: 563 564 Intel PT sample size (%zu) may be too small for PSB period (%zu) 565 566The calculation used for that is: if sample_size <= psb_period + 256 display the 567warning. When sampling is used, psb_period defaults to 0 (2KiB). 568 569The default sample size is 4KiB. 570 571The sample size is passed in aux_sample_size in struct perf_event_attr. The 572sample size is limited by the maximum event size which is 64KiB. It is 573difficult to know how big the event might be without the trace sample attached, 574but the tool validates that the sample size is not greater than 60KiB. 575 576 577new snapshot option 578~~~~~~~~~~~~~~~~~~~ 579 580The difference between full trace and snapshot from the kernel's perspective is 581that in full trace we don't overwrite trace data that the user hasn't collected 582yet (and indicated that by advancing aux_tail), whereas in snapshot mode we let 583the trace run and overwrite older data in the buffer so that whenever something 584interesting happens, we can stop it and grab a snapshot of what was going on 585around that interesting moment. 586 587To select snapshot mode a new option has been added: 588 589 -S 590 591Optionally it can be followed by the snapshot size e.g. 592 593 -S0x100000 594 595The default snapshot size is the auxtrace mmap size. If neither auxtrace mmap size 596nor snapshot size is specified, then the default is 4MiB for privileged users 597(or if /proc/sys/kernel/perf_event_paranoid < 0), 128KiB for unprivileged users. 598If an unprivileged user does not specify mmap pages, the mmap pages will be 599reduced as described in the 'new auxtrace mmap size option' section below. 600 601The snapshot size is displayed if the option -vv is used e.g. 602 603 Intel PT snapshot size: %zu 604 605 606new auxtrace mmap size option 607~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 608 609Intel PT buffer size is specified by an addition to the -m option e.g. 610 611 -m,16 612 613selects a buffer size of 16 pages i.e. 64KiB. 614 615Note that the existing functionality of -m is unchanged. The auxtrace mmap size 616is specified by the optional addition of a comma and the value. 617 618The default auxtrace mmap size for Intel PT is 4MiB/page_size for privileged users 619(or if /proc/sys/kernel/perf_event_paranoid < 0), 128KiB for unprivileged users. 620If an unprivileged user does not specify mmap pages, the mmap pages will be 621reduced from the default 512KiB/page_size to 256KiB/page_size, otherwise the 622user is likely to get an error as they exceed their mlock limit (Max locked 623memory as shown in /proc/self/limits). Note that perf does not count the first 624512KiB (actually /proc/sys/kernel/perf_event_mlock_kb minus 1 page) per cpu 625against the mlock limit so an unprivileged user is allowed 512KiB per cpu plus 626their mlock limit (which defaults to 64KiB but is not multiplied by the number 627of cpus). 628 629In full-trace mode, powers of two are allowed for buffer size, with a minimum 630size of 2 pages. In snapshot mode or sampling mode, it is the same but the 631minimum size is 1 page. 632 633The mmap size and auxtrace mmap size are displayed if the -vv option is used e.g. 634 635 mmap length 528384 636 auxtrace mmap length 4198400 637 638 639Intel PT modes of operation 640~~~~~~~~~~~~~~~~~~~~~~~~~~~ 641 642Intel PT can be used in 3 modes: 643 full-trace mode 644 sample mode 645 snapshot mode 646 647Full-trace mode traces continuously e.g. 648 649 perf record -e intel_pt//u uname 650 651Sample mode attaches a Intel PT sample to other events e.g. 652 653 perf record --aux-sample -e intel_pt//u -e branch-misses:u 654 655Snapshot mode captures the available data when a signal is sent or "snapshot" 656control command is issued. e.g. using a signal 657 658 perf record -v -e intel_pt//u -S ./loopy 1000000000 & 659 [1] 11435 660 kill -USR2 11435 661 Recording AUX area tracing snapshot 662 663Note that the signal sent is SIGUSR2. 664Note that "Recording AUX area tracing snapshot" is displayed because the -v 665option is used. 666 667The advantage of using "snapshot" control command is that the access is 668controlled by access to a FIFO e.g. 669 670 $ mkfifo perf.control 671 $ mkfifo perf.ack 672 $ cat perf.ack & 673 [1] 15235 674 $ sudo ~/bin/perf record --control fifo:perf.control,perf.ack -S -e intel_pt//u -- sleep 60 & 675 [2] 15243 676 $ ps -e | grep perf 677 15244 pts/1 00:00:00 perf 678 $ kill -USR2 15244 679 bash: kill: (15244) - Operation not permitted 680 $ echo snapshot > perf.control 681 ack 682 683The 3 Intel PT modes of operation cannot be used together. 684 685 686Buffer handling 687~~~~~~~~~~~~~~~ 688 689There may be buffer limitations (i.e. single ToPa entry) which means that actual 690buffer sizes are limited to powers of 2 up to 4MiB (MAX_PAGE_ORDER). In order to 691provide other sizes, and in particular an arbitrarily large size, multiple 692buffers are logically concatenated. However an interrupt must be used to switch 693between buffers. That has two potential problems: 694 a) the interrupt may not be handled in time so that the current buffer 695 becomes full and some trace data is lost. 696 b) the interrupts may slow the system and affect the performance 697 results. 698 699If trace data is lost, the driver sets 'truncated' in the PERF_RECORD_AUX event 700which the tools report as an error. 701 702In full-trace mode, the driver waits for data to be copied out before allowing 703the (logical) buffer to wrap-around. If data is not copied out quickly enough, 704again 'truncated' is set in the PERF_RECORD_AUX event. If the driver has to 705wait, the intel_pt event gets disabled. Because it is difficult to know when 706that happens, perf tools always re-enable the intel_pt event after copying out 707data. 708 709 710Intel PT and build ids 711~~~~~~~~~~~~~~~~~~~~~~ 712 713By default "perf record" post-processes the event stream to find all build ids 714for executables for all addresses sampled. Deliberately, Intel PT is not 715decoded for that purpose (it would take too long). Instead the build ids for 716all executables encountered (due to mmap, comm or task events) are included 717in the perf.data file. 718 719To see buildids included in the perf.data file use the command: 720 721 perf buildid-list 722 723If the perf.data file contains Intel PT data, that is the same as: 724 725 perf buildid-list --with-hits 726 727 728Snapshot mode and event disabling 729~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 730 731In order to make a snapshot, the intel_pt event is disabled using an IOCTL, 732namely PERF_EVENT_IOC_DISABLE. However doing that can also disable the 733collection of side-band information. In order to prevent that, a dummy 734software event has been introduced that permits tracking events (like mmaps) to 735continue to be recorded while intel_pt is disabled. That is important to ensure 736there is complete side-band information to allow the decoding of subsequent 737snapshots. 738 739A test has been created for that. To find the test: 740 741 perf test list 742 ... 743 23: Test using a dummy software event to keep tracking 744 745To run the test: 746 747 perf test 23 748 23: Test using a dummy software event to keep tracking : Ok 749 750 751perf record modes (nothing new here) 752~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 753 754perf record essentially operates in one of three modes: 755 per thread 756 per cpu 757 workload only 758 759"per thread" mode is selected by -t or by --per-thread (with -p or -u or just a 760workload). 761"per cpu" is selected by -C or -a. 762"workload only" mode is selected by not using the other options but providing a 763command to run (i.e. the workload). 764 765In per-thread mode an exact list of threads is traced. There is no inheritance. 766Each thread has its own event buffer. 767 768In per-cpu mode all processes (or processes from the selected cgroup i.e. -G 769option, or processes selected with -p or -u) are traced. Each cpu has its own 770buffer. Inheritance is allowed. 771 772In workload-only mode, the workload is traced but with per-cpu buffers. 773Inheritance is allowed. Note that you can now trace a workload in per-thread 774mode by using the --per-thread option. 775 776 777Privileged vs non-privileged users 778~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 779 780Unless /proc/sys/kernel/perf_event_paranoid is set to -1, unprivileged users 781have memory limits imposed upon them. That affects what buffer sizes they can 782have as outlined above. 783 784The v4.2 kernel introduced support for a context switch metadata event, 785PERF_RECORD_SWITCH, which allows unprivileged users to see when their processes 786are scheduled out and in, just not by whom, which is left for the 787PERF_RECORD_SWITCH_CPU_WIDE, that is only accessible in system wide context, 788which in turn requires CAP_PERFMON or CAP_SYS_ADMIN. 789 790Please see the 45ac1403f564 ("perf: Add PERF_RECORD_SWITCH to indicate context 791switches") commit, that introduces these metadata events for further info. 792 793When working with kernels < v4.2, the following considerations must be taken, 794as the sched:sched_switch tracepoints will be used to receive such information: 795 796Unless /proc/sys/kernel/perf_event_paranoid is set to -1, unprivileged users are 797not permitted to use tracepoints which means there is insufficient side-band 798information to decode Intel PT in per-cpu mode, and potentially workload-only 799mode too if the workload creates new processes. 800 801Note also, that to use tracepoints, read-access to debugfs is required. So if 802debugfs is not mounted or the user does not have read-access, it will again not 803be possible to decode Intel PT in per-cpu mode. 804 805 806sched_switch tracepoint 807~~~~~~~~~~~~~~~~~~~~~~~ 808 809The sched_switch tracepoint is used to provide side-band data for Intel PT 810decoding in kernels where the PERF_RECORD_SWITCH metadata event isn't 811available. 812 813The sched_switch events are automatically added. e.g. the second event shown 814below: 815 816 $ perf record -vv -e intel_pt//u uname 817 ------------------------------------------------------------ 818 perf_event_attr: 819 type 6 820 size 112 821 config 0x400 822 { sample_period, sample_freq } 1 823 sample_type IP|TID|TIME|CPU|IDENTIFIER 824 read_format ID 825 disabled 1 826 inherit 1 827 exclude_kernel 1 828 exclude_hv 1 829 enable_on_exec 1 830 sample_id_all 1 831 ------------------------------------------------------------ 832 sys_perf_event_open: pid 31104 cpu 0 group_fd -1 flags 0x8 833 sys_perf_event_open: pid 31104 cpu 1 group_fd -1 flags 0x8 834 sys_perf_event_open: pid 31104 cpu 2 group_fd -1 flags 0x8 835 sys_perf_event_open: pid 31104 cpu 3 group_fd -1 flags 0x8 836 ------------------------------------------------------------ 837 perf_event_attr: 838 type 2 839 size 112 840 config 0x108 841 { sample_period, sample_freq } 1 842 sample_type IP|TID|TIME|CPU|PERIOD|RAW|IDENTIFIER 843 read_format ID 844 inherit 1 845 sample_id_all 1 846 exclude_guest 1 847 ------------------------------------------------------------ 848 sys_perf_event_open: pid -1 cpu 0 group_fd -1 flags 0x8 849 sys_perf_event_open: pid -1 cpu 1 group_fd -1 flags 0x8 850 sys_perf_event_open: pid -1 cpu 2 group_fd -1 flags 0x8 851 sys_perf_event_open: pid -1 cpu 3 group_fd -1 flags 0x8 852 ------------------------------------------------------------ 853 perf_event_attr: 854 type 1 855 size 112 856 config 0x9 857 { sample_period, sample_freq } 1 858 sample_type IP|TID|TIME|IDENTIFIER 859 read_format ID 860 disabled 1 861 inherit 1 862 exclude_kernel 1 863 exclude_hv 1 864 mmap 1 865 comm 1 866 enable_on_exec 1 867 task 1 868 sample_id_all 1 869 mmap2 1 870 comm_exec 1 871 ------------------------------------------------------------ 872 sys_perf_event_open: pid 31104 cpu 0 group_fd -1 flags 0x8 873 sys_perf_event_open: pid 31104 cpu 1 group_fd -1 flags 0x8 874 sys_perf_event_open: pid 31104 cpu 2 group_fd -1 flags 0x8 875 sys_perf_event_open: pid 31104 cpu 3 group_fd -1 flags 0x8 876 mmap size 528384B 877 AUX area mmap length 4194304 878 perf event ring buffer mmapped per cpu 879 Synthesizing auxtrace information 880 Linux 881 [ perf record: Woken up 1 times to write data ] 882 [ perf record: Captured and wrote 0.042 MB perf.data ] 883 884Note, the sched_switch event is only added if the user is permitted to use it 885and only in per-cpu mode. 886 887Note also, the sched_switch event is only added if TSC packets are requested. 888That is because, in the absence of timing information, the sched_switch events 889cannot be matched against the Intel PT trace. 890 891 892perf script 893----------- 894 895By default, perf script will decode trace data found in the perf.data file. 896This can be further controlled by new option --itrace. 897 898 899New --itrace option 900~~~~~~~~~~~~~~~~~~~ 901 902Having no option is the same as 903 904 --itrace 905 906which, in turn, is the same as 907 908 --itrace=cepwxy 909 910The letters are: 911 912 i synthesize "instructions" events 913 y synthesize "cycles" events 914 b synthesize "branches" events 915 x synthesize "transactions" events 916 w synthesize "ptwrite" events 917 p synthesize "power" events (incl. PSB events) 918 c synthesize branches events (calls only) 919 r synthesize branches events (returns only) 920 o synthesize PEBS-via-PT events 921 I synthesize Event Trace events 922 e synthesize tracing error events 923 d create a debug log 924 g synthesize a call chain (use with i or x) 925 G synthesize a call chain on existing event records 926 l synthesize last branch entries (use with i or x) 927 L synthesize last branch entries on existing event records 928 s skip initial number of events 929 q quicker (less detailed) decoding 930 A approximate IPC 931 Z prefer to ignore timestamps (so-called "timeless" decoding) 932 933"Instructions" events look like they were recorded by "perf record -e 934instructions". 935 936"Cycles" events look like they were recorded by "perf record -e cycles" 937(ie., the default). Note that even with CYC packets enabled and no sampling, 938these are not fully accurate, since CYC packets are not emitted for each 939instruction, only when some other event (like an indirect branch, or a 940TNT packet representing multiple branches) happens causes a packet to 941be emitted. Thus, it is more effective for attributing cycles to functions 942(and possibly basic blocks) than to individual instructions, although it 943is not even perfect for functions (although it becomes better if the noretcomp 944option is active). 945 946"Branches" events look like they were recorded by "perf record -e branches". "c" 947and "r" can be combined to get calls and returns. 948 949"Transactions" events correspond to the start or end of transactions. The 950'flags' field can be used in perf script to determine whether the event is a 951transaction start, commit or abort. 952 953Note that "instructions", "cycles", "branches" and "transactions" events 954depend on code flow packets which can be disabled by using the config term 955"branch=0". Refer to the config terms section above. 956 957"ptwrite" events record the payload of the ptwrite instruction and whether 958"fup_on_ptw" was used. "ptwrite" events depend on PTWRITE packets which are 959recorded only if the "ptw" config term was used. Refer to the config terms 960section above. perf script "synth" field displays "ptwrite" information like 961this: "ip: 0 payload: 0x123456789abcdef0" where "ip" is 1 if "fup_on_ptw" was 962used. 963 964"Power" events correspond to power event packets and CBR (core-to-bus ratio) 965packets. While CBR packets are always recorded when tracing is enabled, power 966event packets are recorded only if the "pwr_evt" config term was used. Refer to 967the config terms section above. The power events record information about 968C-state changes, whereas CBR is indicative of CPU frequency. perf script 969"event,synth" fields display information like this: 970 971 cbr: cbr: 22 freq: 2189 MHz (200%) 972 mwait: hints: 0x60 extensions: 0x1 973 pwre: hw: 0 cstate: 2 sub-cstate: 0 974 exstop: ip: 1 975 pwrx: deepest cstate: 2 last cstate: 2 wake reason: 0x4 976 977Where: 978 979 "cbr" includes the frequency and the percentage of maximum non-turbo 980 "mwait" shows mwait hints and extensions 981 "pwre" shows C-state transitions (to a C-state deeper than C0) and 982 whether initiated by hardware 983 "exstop" indicates execution stopped and whether the IP was recorded 984 exactly, 985 "pwrx" indicates return to C0 986 987For more details refer to the Intel 64 and IA-32 Architectures Software 988Developer Manuals. 989 990PSB events show when a PSB+ occurred and also the byte-offset in the trace. 991Emitting a PSB+ can cause a CPU a slight delay. When doing timing analysis 992of code with Intel PT, it is useful to know if a timing bubble was caused 993by Intel PT or not. 994 995Error events show where the decoder lost the trace. Error events 996are quite important. Users must know if what they are seeing is a complete 997picture or not. The "e" option may be followed by flags which affect what errors 998will or will not be reported. Each flag must be preceded by either '+' or '-'. 999The flags supported by Intel PT are: 1000 1001 -o Suppress overflow errors 1002 -l Suppress trace data lost errors 1003 1004For example, for errors but not overflow or data lost errors: 1005 1006 --itrace=e-o-l 1007 1008The "d" option will cause the creation of a file "intel_pt.log" containing all 1009decoded packets and instructions. Note that this option slows down the decoder 1010and that the resulting file may be very large. The "d" option may be followed 1011by flags which affect what debug messages will or will not be logged. Each flag 1012must be preceded by either '+' or '-'. The flags support by Intel PT are: 1013 1014 -a Suppress logging of perf events 1015 +a Log all perf events 1016 +e Output only on decoding errors (size configurable) 1017 +o Output to stdout instead of "intel_pt.log" 1018 1019By default, logged perf events are filtered by any specified time ranges, but 1020flag +a overrides that. The +e flag can be useful for analyzing errors. By 1021default, the log size in that case is 16384 bytes, but can be altered by 1022linkperf:perf-config[1] e.g. perf config itrace.debug-log-buffer-size=30000 1023 1024In addition, the period of the "instructions" event can be specified. e.g. 1025 1026 --itrace=i10us 1027 1028sets the period to 10us i.e. one instruction sample is synthesized for each 10 1029microseconds of trace. Alternatives to "us" are "ms" (milliseconds), 1030"ns" (nanoseconds), "t" (TSC ticks) or "i" (instructions). 1031 1032"ms", "us" and "ns" are converted to TSC ticks. 1033 1034The timing information included with Intel PT does not give the time of every 1035instruction. Consequently, for the purpose of sampling, the decoder estimates 1036the time since the last timing packet based on 1 tick per instruction. The time 1037on the sample is *not* adjusted and reflects the last known value of TSC. 1038 1039For Intel PT, the default period is 100us. 1040 1041Setting it to a zero period means "as often as possible". 1042 1043In the case of Intel PT that is the same as a period of 1 and a unit of 1044'instructions' (i.e. --itrace=i1i). 1045 1046Also the call chain size (default 16, max. 1024) for instructions or 1047transactions events can be specified. e.g. 1048 1049 --itrace=ig32 1050 --itrace=xg32 1051 1052Also the number of last branch entries (default 64, max. 1024) for instructions or 1053transactions events can be specified. e.g. 1054 1055 --itrace=il10 1056 --itrace=xl10 1057 1058Note that last branch entries are cleared for each sample, so there is no overlap 1059from one sample to the next. 1060 1061The G and L options are designed in particular for sample mode, and work much 1062like g and l but add call chain and branch stack to the other selected events 1063instead of synthesized events. For example, to record branch-misses events for 1064'ls' and then add a call chain derived from the Intel PT trace: 1065 1066 perf record --aux-sample -e '{intel_pt//u,branch-misses:u}' -- ls 1067 perf report --itrace=Ge 1068 1069Although in fact G is a default for perf report, so that is the same as just: 1070 1071 perf report 1072 1073One caveat with the G and L options is that they work poorly with "Large PEBS". 1074Large PEBS means PEBS records will be accumulated by hardware and the written 1075into the event buffer in one go. That reduces interrupts, but can give very 1076late timestamps. Because the Intel PT trace is synchronized by timestamps, 1077the PEBS events do not match the trace. Currently, Large PEBS is used only in 1078certain circumstances: 1079 - hardware supports it 1080 - PEBS is used 1081 - event period is specified, instead of frequency 1082 - the sample type is limited to the following flags: 1083 PERF_SAMPLE_IP | PERF_SAMPLE_TID | PERF_SAMPLE_ADDR | 1084 PERF_SAMPLE_ID | PERF_SAMPLE_CPU | PERF_SAMPLE_STREAM_ID | 1085 PERF_SAMPLE_DATA_SRC | PERF_SAMPLE_IDENTIFIER | 1086 PERF_SAMPLE_TRANSACTION | PERF_SAMPLE_PHYS_ADDR | 1087 PERF_SAMPLE_REGS_INTR | PERF_SAMPLE_REGS_USER | 1088 PERF_SAMPLE_PERIOD (and sometimes) | PERF_SAMPLE_TIME 1089Because Intel PT sample mode uses a different sample type to the list above, 1090Large PEBS is not used with Intel PT sample mode. To avoid Large PEBS in other 1091cases, avoid specifying the event period i.e. avoid the 'perf record' -c option, 1092--count option, or 'period' config term. 1093 1094To disable trace decoding entirely, use the option --no-itrace. 1095 1096It is also possible to skip events generated (instructions, branches, transactions) 1097at the beginning. This is useful to ignore initialization code. 1098 1099 --itrace=i0nss1000000 1100 1101skips the first million instructions. 1102 1103The q option changes the way the trace is decoded. The decoding is much faster 1104but much less detailed. Specifically, with the q option, the decoder does not 1105decode TNT packets, and does not walk object code, but gets the ip from FUP and 1106TIP packets. The q option can be used with the b and i options but the period 1107is not used. The q option decodes more quickly, but is useful only if the 1108control flow of interest is represented or indicated by FUP, TIP, TIP.PGE, or 1109TIP.PGD packets (refer below). However the q option could be used to find time 1110ranges that could then be decoded fully using the --time option. 1111 1112What will *not* be decoded with the (single) q option: 1113 1114 - direct calls and jmps 1115 - conditional branches 1116 - non-branch instructions 1117 1118What *will* be decoded with the (single) q option: 1119 1120 - asynchronous branches such as interrupts 1121 - indirect branches 1122 - function return target address *if* the noretcomp config term (refer 1123 config terms section) was used 1124 - start of (control-flow) tracing 1125 - end of (control-flow) tracing, if it is not out of context 1126 - power events, ptwrite, transaction start and abort 1127 - instruction pointer associated with PSB packets 1128 1129Note the q option does not specify what events will be synthesized e.g. the p 1130option must be used also to show power events. 1131 1132Repeating the q option (double-q i.e. qq) results in even faster decoding and even 1133less detail. The decoder decodes only extended PSB (PSB+) packets, getting the 1134instruction pointer if there is a FUP packet within PSB+ (i.e. between PSB and 1135PSBEND). Note PSB packets occur regularly in the trace based on the psb_period 1136config term (refer config terms section). There will be a FUP packet if the 1137PSB+ occurs while control flow is being traced. 1138 1139What will *not* be decoded with the qq option: 1140 1141 - everything except instruction pointer associated with PSB packets 1142 1143What *will* be decoded with the qq option: 1144 1145 - instruction pointer associated with PSB packets 1146 1147The Z option is equivalent to having recorded a trace without TSC 1148(i.e. config term tsc=0). It can be useful to avoid timestamp issues when 1149decoding a trace of a virtual machine. 1150 1151 1152dlfilter-show-cycles.so 1153~~~~~~~~~~~~~~~~~~~~~~~ 1154 1155Cycles can be displayed using dlfilter-show-cycles.so in which case the itrace A 1156option can be useful to provide higher granularity cycle information: 1157 1158 perf script --itrace=A --call-trace --dlfilter dlfilter-show-cycles.so 1159 1160To see a list of dlfilters: 1161 1162 perf script -v --list-dlfilters 1163 1164See also linkperf:perf-dlfilters[1] 1165 1166 1167dump option 1168~~~~~~~~~~~ 1169 1170perf script has an option (-D) to "dump" the events i.e. display the binary 1171data. 1172 1173When -D is used, Intel PT packets are displayed. The packet decoder does not 1174pay attention to PSB packets, but just decodes the bytes - so the packets seen 1175by the actual decoder may not be identical in places where the data is corrupt. 1176One example of that would be when the buffer-switching interrupt has been too 1177slow, and the buffer has been filled completely. In that case, the last packet 1178in the buffer might be truncated and immediately followed by a PSB as the trace 1179continues in the next buffer. 1180 1181To disable the display of Intel PT packets, combine the -D option with 1182--no-itrace. 1183 1184 1185perf report 1186----------- 1187 1188By default, perf report will decode trace data found in the perf.data file. 1189This can be further controlled by new option --itrace exactly the same as 1190perf script, with the exception that the default is --itrace=igxe. 1191 1192 1193perf inject 1194----------- 1195 1196perf inject also accepts the --itrace option in which case tracing data is 1197removed and replaced with the synthesized events. e.g. 1198 1199 perf inject --itrace -i perf.data -o perf.data.new 1200 1201Below is an example of using Intel PT with autofdo. It requires autofdo 1202(https://github.com/google/autofdo) and gcc version 5. The bubble 1203sort example is from the AutoFDO tutorial (https://gcc.gnu.org/wiki/AutoFDO/Tutorial) 1204amended to take the number of elements as a parameter. 1205 1206 $ gcc-5 -O3 sort.c -o sort_optimized 1207 $ ./sort_optimized 30000 1208 Bubble sorting array of 30000 elements 1209 2254 ms 1210 1211 $ cat ~/.perfconfig 1212 [intel-pt] 1213 mispred-all = on 1214 1215 $ perf record -e intel_pt//u ./sort 3000 1216 Bubble sorting array of 3000 elements 1217 58 ms 1218 [ perf record: Woken up 2 times to write data ] 1219 [ perf record: Captured and wrote 3.939 MB perf.data ] 1220 $ perf inject -i perf.data -o inj --itrace=i100usle --strip 1221 $ ./create_gcov --binary=./sort --profile=inj --gcov=sort.gcov -gcov_version=1 1222 $ gcc-5 -O3 -fauto-profile=sort.gcov sort.c -o sort_autofdo 1223 $ ./sort_autofdo 30000 1224 Bubble sorting array of 30000 elements 1225 2155 ms 1226 1227Note there is currently no advantage to using Intel PT instead of LBR, but 1228that may change in the future if greater use is made of the data. 1229 1230 1231PEBS via Intel PT 1232----------------- 1233 1234Some hardware has the feature to redirect PEBS records to the Intel PT trace. 1235Recording is selected by using the aux-output config term e.g. 1236 1237 perf record -c 10000 -e '{intel_pt/branch=0/,cycles/aux-output/ppp}' uname 1238 1239Originally, software only supported redirecting at most one PEBS event because it 1240was not able to differentiate one event from another. To overcome that, more recent 1241kernels and perf tools add support for the PERF_RECORD_AUX_OUTPUT_HW_ID side-band event. 1242To check for the presence of that event in a PEBS-via-PT trace: 1243 1244 perf script -D --no-itrace | grep PERF_RECORD_AUX_OUTPUT_HW_ID 1245 1246To display PEBS events from the Intel PT trace, use the itrace 'o' option e.g. 1247 1248 perf script --itrace=oe 1249 1250XED 1251--- 1252 1253include::build-xed.txt[] 1254 1255 1256Tracing Virtual Machines (kernel only) 1257-------------------------------------- 1258 1259Currently, kernel tracing is supported with either "timeless" decoding 1260(i.e. no TSC timestamps) or VM Time Correlation. VM Time Correlation is an extra step 1261using 'perf inject' and requires unchanging VMX TSC Offset and no VMX TSC Scaling. 1262 1263Other limitations and caveats 1264 1265 VMX controls may suppress packets needed for decoding resulting in decoding errors 1266 VMX controls may block the perf NMI to the host potentially resulting in lost trace data 1267 Guest kernel self-modifying code (e.g. jump labels or JIT-compiled eBPF) will result in decoding errors 1268 Guest thread information is unknown 1269 Guest VCPU is unknown but may be able to be inferred from the host thread 1270 Callchains are not supported 1271 1272Example using "timeless" decoding 1273 1274Start VM 1275 1276 $ sudo virsh start kubuntu20.04 1277 Domain kubuntu20.04 started 1278 1279Mount the guest file system. Note sshfs needs -o direct_io to enable reading of proc files. root access is needed to read /proc/kcore. 1280 1281 $ mkdir vm0 1282 $ sshfs -o direct_io root@vm0:/ vm0 1283 1284Copy the guest /proc/kallsyms, /proc/modules and /proc/kcore 1285 1286 $ perf buildid-cache -v --kcore vm0/proc/kcore 1287 kcore added to build-id cache directory /home/user/.debug/[kernel.kcore]/9600f316a53a0f54278885e8d9710538ec5f6a08/2021021807494306 1288 $ KALLSYMS=/home/user/.debug/[kernel.kcore]/9600f316a53a0f54278885e8d9710538ec5f6a08/2021021807494306/kallsyms 1289 1290Find the VM process 1291 1292 $ ps -eLl | grep 'KVM\|PID' 1293 F S UID PID PPID LWP C PRI NI ADDR SZ WCHAN TTY TIME CMD 1294 3 S 64055 1430 1 1440 1 80 0 - 1921718 - ? 00:02:47 CPU 0/KVM 1295 3 S 64055 1430 1 1441 1 80 0 - 1921718 - ? 00:02:41 CPU 1/KVM 1296 3 S 64055 1430 1 1442 1 80 0 - 1921718 - ? 00:02:38 CPU 2/KVM 1297 3 S 64055 1430 1 1443 2 80 0 - 1921718 - ? 00:03:18 CPU 3/KVM 1298 1299Start an open-ended perf record, tracing the VM process, do something on the VM, and then ctrl-C to stop. 1300TSC is not supported and tsc=0 must be specified. That means mtc is useless, so add mtc=0. 1301However, IPC can still be determined, hence cyc=1 can be added. 1302Only kernel decoding is supported, so 'k' must be specified. 1303Intel PT traces both the host and the guest so --guest and --host need to be specified. 1304Without timestamps, --per-thread must be specified to distinguish threads. 1305 1306 $ sudo perf kvm --guest --host --guestkallsyms $KALLSYMS record --kcore -e intel_pt/tsc=0,mtc=0,cyc=1/k -p 1430 --per-thread 1307 ^C 1308 [ perf record: Woken up 1 times to write data ] 1309 [ perf record: Captured and wrote 5.829 MB ] 1310 1311perf script can be used to provide an instruction trace 1312 1313 $ perf script --guestkallsyms $KALLSYMS --insn-trace=disasm -F+ipc | grep -C10 vmresume | head -21 1314 CPU 0/KVM 1440 ffffffff82133cdd __vmx_vcpu_run+0x3d ([kernel.kallsyms]) movq 0x48(%rax), %r9 1315 CPU 0/KVM 1440 ffffffff82133ce1 __vmx_vcpu_run+0x41 ([kernel.kallsyms]) movq 0x50(%rax), %r10 1316 CPU 0/KVM 1440 ffffffff82133ce5 __vmx_vcpu_run+0x45 ([kernel.kallsyms]) movq 0x58(%rax), %r11 1317 CPU 0/KVM 1440 ffffffff82133ce9 __vmx_vcpu_run+0x49 ([kernel.kallsyms]) movq 0x60(%rax), %r12 1318 CPU 0/KVM 1440 ffffffff82133ced __vmx_vcpu_run+0x4d ([kernel.kallsyms]) movq 0x68(%rax), %r13 1319 CPU 0/KVM 1440 ffffffff82133cf1 __vmx_vcpu_run+0x51 ([kernel.kallsyms]) movq 0x70(%rax), %r14 1320 CPU 0/KVM 1440 ffffffff82133cf5 __vmx_vcpu_run+0x55 ([kernel.kallsyms]) movq 0x78(%rax), %r15 1321 CPU 0/KVM 1440 ffffffff82133cf9 __vmx_vcpu_run+0x59 ([kernel.kallsyms]) movq (%rax), %rax 1322 CPU 0/KVM 1440 ffffffff82133cfc __vmx_vcpu_run+0x5c ([kernel.kallsyms]) callq 0xffffffff82133c40 1323 CPU 0/KVM 1440 ffffffff82133c40 vmx_vmenter+0x0 ([kernel.kallsyms]) jz 0xffffffff82133c46 1324 CPU 0/KVM 1440 ffffffff82133c42 vmx_vmenter+0x2 ([kernel.kallsyms]) vmresume IPC: 0.11 (50/445) 1325 :1440 1440 ffffffffbb678b06 native_write_msr+0x6 ([guest.kernel.kallsyms]) nopl %eax, (%rax,%rax,1) 1326 :1440 1440 ffffffffbb678b0b native_write_msr+0xb ([guest.kernel.kallsyms]) retq IPC: 0.04 (2/41) 1327 :1440 1440 ffffffffbb666646 lapic_next_deadline+0x26 ([guest.kernel.kallsyms]) data16 nop 1328 :1440 1440 ffffffffbb666648 lapic_next_deadline+0x28 ([guest.kernel.kallsyms]) xor %eax, %eax 1329 :1440 1440 ffffffffbb66664a lapic_next_deadline+0x2a ([guest.kernel.kallsyms]) popq %rbp 1330 :1440 1440 ffffffffbb66664b lapic_next_deadline+0x2b ([guest.kernel.kallsyms]) retq IPC: 0.16 (4/25) 1331 :1440 1440 ffffffffbb74607f clockevents_program_event+0x8f ([guest.kernel.kallsyms]) test %eax, %eax 1332 :1440 1440 ffffffffbb746081 clockevents_program_event+0x91 ([guest.kernel.kallsyms]) jz 0xffffffffbb74603c IPC: 0.06 (2/30) 1333 :1440 1440 ffffffffbb74603c clockevents_program_event+0x4c ([guest.kernel.kallsyms]) popq %rbx 1334 :1440 1440 ffffffffbb74603d clockevents_program_event+0x4d ([guest.kernel.kallsyms]) popq %r12 1335 1336Example using VM Time Correlation 1337 1338Start VM 1339 1340 $ sudo virsh start kubuntu20.04 1341 Domain kubuntu20.04 started 1342 1343Mount the guest file system. Note sshfs needs -o direct_io to enable reading of proc files. root access is needed to read /proc/kcore. 1344 1345 $ mkdir -p vm0 1346 $ sshfs -o direct_io root@vm0:/ vm0 1347 1348Copy the guest /proc/kallsyms, /proc/modules and /proc/kcore 1349 1350 $ perf buildid-cache -v --kcore vm0/proc/kcore 1351 same kcore found in /home/user/.debug/[kernel.kcore]/cc9c55a98c5e4ec0aeda69302554aabed5cd6491/2021021312450777 1352 $ KALLSYMS=/home/user/.debug/\[kernel.kcore\]/cc9c55a98c5e4ec0aeda69302554aabed5cd6491/2021021312450777/kallsyms 1353 1354Find the VM process 1355 1356 $ ps -eLl | grep 'KVM\|PID' 1357 F S UID PID PPID LWP C PRI NI ADDR SZ WCHAN TTY TIME CMD 1358 3 S 64055 16998 1 17005 13 80 0 - 1818189 - ? 00:00:16 CPU 0/KVM 1359 3 S 64055 16998 1 17006 4 80 0 - 1818189 - ? 00:00:05 CPU 1/KVM 1360 3 S 64055 16998 1 17007 3 80 0 - 1818189 - ? 00:00:04 CPU 2/KVM 1361 3 S 64055 16998 1 17008 4 80 0 - 1818189 - ? 00:00:05 CPU 3/KVM 1362 1363Start an open-ended perf record, tracing the VM process, do something on the VM, and then ctrl-C to stop. 1364IPC can be determined, hence cyc=1 can be added. 1365Only kernel decoding is supported, so 'k' must be specified. 1366Intel PT traces both the host and the guest so --guest and --host need to be specified. 1367 1368 $ sudo perf kvm --guest --host --guestkallsyms $KALLSYMS record --kcore -e intel_pt/cyc=1/k -p 16998 1369 ^C[ perf record: Woken up 1 times to write data ] 1370 [ perf record: Captured and wrote 9.041 MB perf.data.kvm ] 1371 1372Now 'perf inject' can be used to determine the VMX TCS Offset. Note, Intel PT TSC packets are 1373only 7-bytes, so the TSC Offset might differ from the actual value in the 8th byte. That will 1374have no effect i.e. the resulting timestamps will be correct anyway. 1375 1376 $ perf inject -i perf.data.kvm --vm-time-correlation=dry-run 1377 ERROR: Unknown TSC Offset for VMCS 0x1bff6a 1378 VMCS: 0x1bff6a TSC Offset 0xffffe42722c64c41 1379 ERROR: Unknown TSC Offset for VMCS 0x1cbc08 1380 VMCS: 0x1cbc08 TSC Offset 0xffffe42722c64c41 1381 ERROR: Unknown TSC Offset for VMCS 0x1c3ce8 1382 VMCS: 0x1c3ce8 TSC Offset 0xffffe42722c64c41 1383 ERROR: Unknown TSC Offset for VMCS 0x1cbce9 1384 VMCS: 0x1cbce9 TSC Offset 0xffffe42722c64c41 1385 1386Each virtual CPU has a different Virtual Machine Control Structure (VMCS) 1387shown above with the calculated TSC Offset. For an unchanging TSC Offset 1388they should all be the same for the same virtual machine. 1389 1390Now that the TSC Offset is known, it can be provided to 'perf inject' 1391 1392 $ perf inject -i perf.data.kvm --vm-time-correlation="dry-run 0xffffe42722c64c41" 1393 1394Note the options for 'perf inject' --vm-time-correlation are: 1395 1396 [ dry-run ] [ <TSC Offset> [ : <VMCS> [ , <VMCS> ]... ] ]... 1397 1398So it is possible to specify different TSC Offsets for different VMCS. 1399The option "dry-run" will cause the file to be processed but without updating it. 1400Note it is also possible to get a intel_pt.log file by adding option --itrace=d 1401 1402There were no errors so, do it for real 1403 1404 $ perf inject -i perf.data.kvm --vm-time-correlation=0xffffe42722c64c41 --force 1405 1406'perf script' can be used to see if there are any decoder errors 1407 1408 $ perf script -i perf.data.kvm --guestkallsyms $KALLSYMS --itrace=e-o 1409 1410There were none. 1411 1412'perf script' can be used to provide an instruction trace showing timestamps 1413 1414 $ perf script -i perf.data.kvm --guestkallsyms $KALLSYMS --insn-trace=disasm -F+ipc | grep -C10 vmresume | head -21 1415 CPU 1/KVM 17006 [001] 11500.262865593: ffffffff82133cdd __vmx_vcpu_run+0x3d ([kernel.kallsyms]) movq 0x48(%rax), %r9 1416 CPU 1/KVM 17006 [001] 11500.262865593: ffffffff82133ce1 __vmx_vcpu_run+0x41 ([kernel.kallsyms]) movq 0x50(%rax), %r10 1417 CPU 1/KVM 17006 [001] 11500.262865593: ffffffff82133ce5 __vmx_vcpu_run+0x45 ([kernel.kallsyms]) movq 0x58(%rax), %r11 1418 CPU 1/KVM 17006 [001] 11500.262865593: ffffffff82133ce9 __vmx_vcpu_run+0x49 ([kernel.kallsyms]) movq 0x60(%rax), %r12 1419 CPU 1/KVM 17006 [001] 11500.262865593: ffffffff82133ced __vmx_vcpu_run+0x4d ([kernel.kallsyms]) movq 0x68(%rax), %r13 1420 CPU 1/KVM 17006 [001] 11500.262865593: ffffffff82133cf1 __vmx_vcpu_run+0x51 ([kernel.kallsyms]) movq 0x70(%rax), %r14 1421 CPU 1/KVM 17006 [001] 11500.262865593: ffffffff82133cf5 __vmx_vcpu_run+0x55 ([kernel.kallsyms]) movq 0x78(%rax), %r15 1422 CPU 1/KVM 17006 [001] 11500.262865593: ffffffff82133cf9 __vmx_vcpu_run+0x59 ([kernel.kallsyms]) movq (%rax), %rax 1423 CPU 1/KVM 17006 [001] 11500.262865593: ffffffff82133cfc __vmx_vcpu_run+0x5c ([kernel.kallsyms]) callq 0xffffffff82133c40 1424 CPU 1/KVM 17006 [001] 11500.262865593: ffffffff82133c40 vmx_vmenter+0x0 ([kernel.kallsyms]) jz 0xffffffff82133c46 1425 CPU 1/KVM 17006 [001] 11500.262866075: ffffffff82133c42 vmx_vmenter+0x2 ([kernel.kallsyms]) vmresume IPC: 0.05 (40/769) 1426 :17006 17006 [001] 11500.262869216: ffffffff82200cb0 asm_sysvec_apic_timer_interrupt+0x0 ([guest.kernel.kallsyms]) clac 1427 :17006 17006 [001] 11500.262869216: ffffffff82200cb3 asm_sysvec_apic_timer_interrupt+0x3 ([guest.kernel.kallsyms]) pushq $0xffffffffffffffff 1428 :17006 17006 [001] 11500.262869216: ffffffff82200cb5 asm_sysvec_apic_timer_interrupt+0x5 ([guest.kernel.kallsyms]) callq 0xffffffff82201160 1429 :17006 17006 [001] 11500.262869216: ffffffff82201160 error_entry+0x0 ([guest.kernel.kallsyms]) cld 1430 :17006 17006 [001] 11500.262869216: ffffffff82201161 error_entry+0x1 ([guest.kernel.kallsyms]) pushq %rsi 1431 :17006 17006 [001] 11500.262869216: ffffffff82201162 error_entry+0x2 ([guest.kernel.kallsyms]) movq 0x8(%rsp), %rsi 1432 :17006 17006 [001] 11500.262869216: ffffffff82201167 error_entry+0x7 ([guest.kernel.kallsyms]) movq %rdi, 0x8(%rsp) 1433 :17006 17006 [001] 11500.262869216: ffffffff8220116c error_entry+0xc ([guest.kernel.kallsyms]) pushq %rdx 1434 :17006 17006 [001] 11500.262869216: ffffffff8220116d error_entry+0xd ([guest.kernel.kallsyms]) pushq %rcx 1435 :17006 17006 [001] 11500.262869216: ffffffff8220116e error_entry+0xe ([guest.kernel.kallsyms]) pushq %rax 1436 1437 1438Tracing Virtual Machines (including user space) 1439----------------------------------------------- 1440 1441It is possible to use perf record to record sideband events within a virtual machine, so that an Intel PT trace on the host can be decoded. 1442Sideband events from the guest perf.data file can be injected into the host perf.data file using perf inject. 1443 1444Here is an example of the steps needed: 1445 1446On the guest machine: 1447 1448Check that no-kvmclock kernel command line option was used to boot: 1449 1450Note, this is essential to enable time correlation between host and guest machines. 1451 1452 $ cat /proc/cmdline 1453 BOOT_IMAGE=/boot/vmlinuz-5.10.0-16-amd64 root=UUID=cb49c910-e573-47e0-bce7-79e293df8e1d ro no-kvmclock 1454 1455There is no BPF support at present so, if possible, disable JIT compiling: 1456 1457 $ echo 0 | sudo tee /proc/sys/net/core/bpf_jit_enable 1458 0 1459 1460Start perf record to collect sideband events: 1461 1462 $ sudo perf record -o guest-sideband-testing-guest-perf.data --sample-identifier --buildid-all --switch-events --kcore -a -e dummy 1463 1464On the host machine: 1465 1466Start perf record to collect Intel PT trace: 1467 1468Note, the host trace will get very big, very fast, so the steps from starting to stopping the host trace really need to be done so that they happen in the shortest time possible. 1469 1470 $ sudo perf record -o guest-sideband-testing-host-perf.data -m,64M --kcore -a -e intel_pt/cyc/ 1471 1472On the guest machine: 1473 1474Run a small test case, just 'uname' in this example: 1475 1476 $ uname 1477 Linux 1478 1479On the host machine: 1480 1481Stop the Intel PT trace: 1482 1483 ^C 1484 [ perf record: Woken up 1 times to write data ] 1485 [ perf record: Captured and wrote 76.122 MB guest-sideband-testing-host-perf.data ] 1486 1487On the guest machine: 1488 1489Stop the Intel PT trace: 1490 1491 ^C 1492 [ perf record: Woken up 1 times to write data ] 1493 [ perf record: Captured and wrote 1.247 MB guest-sideband-testing-guest-perf.data ] 1494 1495And then copy guest-sideband-testing-guest-perf.data to the host (not shown here). 1496 1497On the host machine: 1498 1499With the 2 perf.data recordings, and with their ownership changed to the user. 1500 1501Identify the TSC Offset: 1502 1503 $ perf inject -i guest-sideband-testing-host-perf.data --vm-time-correlation=dry-run 1504 VMCS: 0x103fc6 TSC Offset 0xfffffa6ae070cb20 1505 VMCS: 0x103ff2 TSC Offset 0xfffffa6ae070cb20 1506 VMCS: 0x10fdaa TSC Offset 0xfffffa6ae070cb20 1507 VMCS: 0x24d57c TSC Offset 0xfffffa6ae070cb20 1508 1509Correct Intel PT TSC timestamps for the guest machine: 1510 1511 $ perf inject -i guest-sideband-testing-host-perf.data --vm-time-correlation=0xfffffa6ae070cb20 --force 1512 1513Identify the guest machine PID: 1514 1515 $ perf script -i guest-sideband-testing-host-perf.data --no-itrace --show-task-events | grep KVM 1516 CPU 0/KVM 0 [000] 0.000000: PERF_RECORD_COMM: CPU 0/KVM:13376/13381 1517 CPU 1/KVM 0 [000] 0.000000: PERF_RECORD_COMM: CPU 1/KVM:13376/13382 1518 CPU 2/KVM 0 [000] 0.000000: PERF_RECORD_COMM: CPU 2/KVM:13376/13383 1519 CPU 3/KVM 0 [000] 0.000000: PERF_RECORD_COMM: CPU 3/KVM:13376/13384 1520 1521Note, the QEMU option -name debug-threads=on is needed so that thread names 1522can be used to determine which thread is running which VCPU as above. libvirt seems to use this by default. 1523 1524Create a guestmount, assuming the guest machine is 'vm_to_test': 1525 1526 $ mkdir -p ~/guestmount/13376 1527 $ sshfs -o direct_io vm_to_test:/ ~/guestmount/13376 1528 1529Inject the guest perf.data file into the host perf.data file: 1530 1531Note, due to the guestmount option, guest object files and debug files will be copied into the build ID cache from the guest machine, with the notable exception of VDSO. 1532If needed, VDSO can be copied manually in a fashion similar to that used by the perf-archive script. 1533 1534 $ perf inject -i guest-sideband-testing-host-perf.data -o inj --guestmount ~/guestmount --guest-data=guest-sideband-testing-guest-perf.data,13376,0xfffffa6ae070cb20 1535 1536Show an excerpt from the result. In this case the CPU and time range have been to chosen to show interaction between guest and host when 'uname' is starting to run on the guest machine: 1537 1538Notes: 1539 1540 - the CPU displayed, [002] in this case, is always the host CPU 1541 - events happening in the virtual machine start with VM:13376 VCPU:003, which shows the hypervisor PID 13376 and the VCPU number 1542 - only calls and errors are displayed i.e. --itrace=ce 1543 - branches entering and exiting the virtual machine are split, and show as 2 branches to/from "0 [unknown] ([unknown])" 1544 1545 $ perf script -i inj --itrace=ce -F+machine_pid,+vcpu,+addr,+pid,+tid,-period --ns --time 7919.408803365,7919.408804631 -C 2 1546 CPU 3/KVM 13376/13384 [002] 7919.408803365: branches: ffffffffc0f8ebe0 vmx_vcpu_enter_exit+0xc0 ([kernel.kallsyms]) => ffffffffc0f8edc0 __vmx_vcpu_run+0x0 ([kernel.kallsyms]) 1547 CPU 3/KVM 13376/13384 [002] 7919.408803365: branches: ffffffffc0f8edd5 __vmx_vcpu_run+0x15 ([kernel.kallsyms]) => ffffffffc0f8eca0 vmx_update_host_rsp+0x0 ([kernel.kallsyms]) 1548 CPU 3/KVM 13376/13384 [002] 7919.408803365: branches: ffffffffc0f8ee1b __vmx_vcpu_run+0x5b ([kernel.kallsyms]) => ffffffffc0f8ed60 vmx_vmenter+0x0 ([kernel.kallsyms]) 1549 CPU 3/KVM 13376/13384 [002] 7919.408803461: branches: ffffffffc0f8ed62 vmx_vmenter+0x2 ([kernel.kallsyms]) => 0 [unknown] ([unknown]) 1550 VM:13376 VCPU:003 uname 3404/3404 [002] 7919.408803461: branches: 0 [unknown] ([unknown]) => 7f851c9b5a5c init_cacheinfo+0x3ac (/usr/lib/x86_64-linux-gnu/libc-2.31.so) 1551 VM:13376 VCPU:003 uname 3404/3404 [002] 7919.408803567: branches: 7f851c9b5a5a init_cacheinfo+0x3aa (/usr/lib/x86_64-linux-gnu/libc-2.31.so) => 0 [unknown] ([unknown]) 1552 CPU 3/KVM 13376/13384 [002] 7919.408803567: branches: 0 [unknown] ([unknown]) => ffffffffc0f8ed80 vmx_vmexit+0x0 ([kernel.kallsyms]) 1553 CPU 3/KVM 13376/13384 [002] 7919.408803596: branches: ffffffffc0f6619a vmx_vcpu_run+0x26a ([kernel.kallsyms]) => ffffffffb2255c60 x86_virt_spec_ctrl+0x0 ([kernel.kallsyms]) 1554 CPU 3/KVM 13376/13384 [002] 7919.408803801: branches: ffffffffc0f66445 vmx_vcpu_run+0x515 ([kernel.kallsyms]) => ffffffffb2290b30 native_write_msr+0x0 ([kernel.kallsyms]) 1555 CPU 3/KVM 13376/13384 [002] 7919.408803850: branches: ffffffffc0f661f8 vmx_vcpu_run+0x2c8 ([kernel.kallsyms]) => ffffffffc1092300 kvm_load_host_xsave_state+0x0 ([kernel.kallsyms]) 1556 CPU 3/KVM 13376/13384 [002] 7919.408803850: branches: ffffffffc1092327 kvm_load_host_xsave_state+0x27 ([kernel.kallsyms]) => ffffffffc1092220 kvm_load_host_xsave_state.part.0+0x0 ([kernel.kallsyms]) 1557 CPU 3/KVM 13376/13384 [002] 7919.408803862: branches: ffffffffc0f662cf vmx_vcpu_run+0x39f ([kernel.kallsyms]) => ffffffffc0f63f90 vmx_recover_nmi_blocking+0x0 ([kernel.kallsyms]) 1558 CPU 3/KVM 13376/13384 [002] 7919.408803862: branches: ffffffffc0f662e9 vmx_vcpu_run+0x3b9 ([kernel.kallsyms]) => ffffffffc0f619a0 __vmx_complete_interrupts+0x0 ([kernel.kallsyms]) 1559 CPU 3/KVM 13376/13384 [002] 7919.408803872: branches: ffffffffc109cfb2 vcpu_enter_guest+0x752 ([kernel.kallsyms]) => ffffffffc0f5f570 vmx_handle_exit_irqoff+0x0 ([kernel.kallsyms]) 1560 CPU 3/KVM 13376/13384 [002] 7919.408803881: branches: ffffffffc109d028 vcpu_enter_guest+0x7c8 ([kernel.kallsyms]) => ffffffffb234f900 __srcu_read_lock+0x0 ([kernel.kallsyms]) 1561 CPU 3/KVM 13376/13384 [002] 7919.408803897: branches: ffffffffc109d06f vcpu_enter_guest+0x80f ([kernel.kallsyms]) => ffffffffc0f72e30 vmx_handle_exit+0x0 ([kernel.kallsyms]) 1562 CPU 3/KVM 13376/13384 [002] 7919.408803897: branches: ffffffffc0f72e3d vmx_handle_exit+0xd ([kernel.kallsyms]) => ffffffffc0f727c0 __vmx_handle_exit+0x0 ([kernel.kallsyms]) 1563 CPU 3/KVM 13376/13384 [002] 7919.408803897: branches: ffffffffc0f72b15 __vmx_handle_exit+0x355 ([kernel.kallsyms]) => ffffffffc0f60ae0 vmx_flush_pml_buffer+0x0 ([kernel.kallsyms]) 1564 CPU 3/KVM 13376/13384 [002] 7919.408803903: branches: ffffffffc0f72994 __vmx_handle_exit+0x1d4 ([kernel.kallsyms]) => ffffffffc10b7090 kvm_emulate_cpuid+0x0 ([kernel.kallsyms]) 1565 CPU 3/KVM 13376/13384 [002] 7919.408803903: branches: ffffffffc10b70f1 kvm_emulate_cpuid+0x61 ([kernel.kallsyms]) => ffffffffc10b6e10 kvm_cpuid+0x0 ([kernel.kallsyms]) 1566 CPU 3/KVM 13376/13384 [002] 7919.408803941: branches: ffffffffc10b7125 kvm_emulate_cpuid+0x95 ([kernel.kallsyms]) => ffffffffc1093110 kvm_skip_emulated_instruction+0x0 ([kernel.kallsyms]) 1567 CPU 3/KVM 13376/13384 [002] 7919.408803941: branches: ffffffffc109311f kvm_skip_emulated_instruction+0xf ([kernel.kallsyms]) => ffffffffc0f5e180 vmx_get_rflags+0x0 ([kernel.kallsyms]) 1568 CPU 3/KVM 13376/13384 [002] 7919.408803951: branches: ffffffffc109312a kvm_skip_emulated_instruction+0x1a ([kernel.kallsyms]) => ffffffffc0f5fd30 vmx_skip_emulated_instruction+0x0 ([kernel.kallsyms]) 1569 CPU 3/KVM 13376/13384 [002] 7919.408803951: branches: ffffffffc0f5fd79 vmx_skip_emulated_instruction+0x49 ([kernel.kallsyms]) => ffffffffc0f5fb50 skip_emulated_instruction+0x0 ([kernel.kallsyms]) 1570 CPU 3/KVM 13376/13384 [002] 7919.408803956: branches: ffffffffc0f5fc68 skip_emulated_instruction+0x118 ([kernel.kallsyms]) => ffffffffc0f6a940 vmx_cache_reg+0x0 ([kernel.kallsyms]) 1571 CPU 3/KVM 13376/13384 [002] 7919.408803964: branches: ffffffffc0f5fc11 skip_emulated_instruction+0xc1 ([kernel.kallsyms]) => ffffffffc0f5f9e0 vmx_set_interrupt_shadow+0x0 ([kernel.kallsyms]) 1572 CPU 3/KVM 13376/13384 [002] 7919.408803980: branches: ffffffffc109f8b1 vcpu_run+0x71 ([kernel.kallsyms]) => ffffffffc10ad2f0 kvm_cpu_has_pending_timer+0x0 ([kernel.kallsyms]) 1573 CPU 3/KVM 13376/13384 [002] 7919.408803980: branches: ffffffffc10ad2fb kvm_cpu_has_pending_timer+0xb ([kernel.kallsyms]) => ffffffffc10b0490 apic_has_pending_timer+0x0 ([kernel.kallsyms]) 1574 CPU 3/KVM 13376/13384 [002] 7919.408803991: branches: ffffffffc109f899 vcpu_run+0x59 ([kernel.kallsyms]) => ffffffffc109c860 vcpu_enter_guest+0x0 ([kernel.kallsyms]) 1575 CPU 3/KVM 13376/13384 [002] 7919.408803993: branches: ffffffffc109cd4c vcpu_enter_guest+0x4ec ([kernel.kallsyms]) => ffffffffc0f69140 vmx_prepare_switch_to_guest+0x0 ([kernel.kallsyms]) 1576 CPU 3/KVM 13376/13384 [002] 7919.408803996: branches: ffffffffc109cd7d vcpu_enter_guest+0x51d ([kernel.kallsyms]) => ffffffffb234f930 __srcu_read_unlock+0x0 ([kernel.kallsyms]) 1577 CPU 3/KVM 13376/13384 [002] 7919.408803996: branches: ffffffffc109cd9c vcpu_enter_guest+0x53c ([kernel.kallsyms]) => ffffffffc0f609b0 vmx_sync_pir_to_irr+0x0 ([kernel.kallsyms]) 1578 CPU 3/KVM 13376/13384 [002] 7919.408803996: branches: ffffffffc0f60a6d vmx_sync_pir_to_irr+0xbd ([kernel.kallsyms]) => ffffffffc10adc20 kvm_lapic_find_highest_irr+0x0 ([kernel.kallsyms]) 1579 CPU 3/KVM 13376/13384 [002] 7919.408804010: branches: ffffffffc0f60abd vmx_sync_pir_to_irr+0x10d ([kernel.kallsyms]) => ffffffffc0f60820 vmx_set_rvi+0x0 ([kernel.kallsyms]) 1580 CPU 3/KVM 13376/13384 [002] 7919.408804019: branches: ffffffffc109ceca vcpu_enter_guest+0x66a ([kernel.kallsyms]) => ffffffffb2249840 fpregs_assert_state_consistent+0x0 ([kernel.kallsyms]) 1581 CPU 3/KVM 13376/13384 [002] 7919.408804021: branches: ffffffffc109cf10 vcpu_enter_guest+0x6b0 ([kernel.kallsyms]) => ffffffffc0f65f30 vmx_vcpu_run+0x0 ([kernel.kallsyms]) 1582 CPU 3/KVM 13376/13384 [002] 7919.408804024: branches: ffffffffc0f6603b vmx_vcpu_run+0x10b ([kernel.kallsyms]) => ffffffffb229bed0 __get_current_cr3_fast+0x0 ([kernel.kallsyms]) 1583 CPU 3/KVM 13376/13384 [002] 7919.408804024: branches: ffffffffc0f66055 vmx_vcpu_run+0x125 ([kernel.kallsyms]) => ffffffffb2253050 cr4_read_shadow+0x0 ([kernel.kallsyms]) 1584 CPU 3/KVM 13376/13384 [002] 7919.408804030: branches: ffffffffc0f6608d vmx_vcpu_run+0x15d ([kernel.kallsyms]) => ffffffffc10921e0 kvm_load_guest_xsave_state+0x0 ([kernel.kallsyms]) 1585 CPU 3/KVM 13376/13384 [002] 7919.408804030: branches: ffffffffc1092207 kvm_load_guest_xsave_state+0x27 ([kernel.kallsyms]) => ffffffffc1092110 kvm_load_guest_xsave_state.part.0+0x0 ([kernel.kallsyms]) 1586 CPU 3/KVM 13376/13384 [002] 7919.408804032: branches: ffffffffc0f660c6 vmx_vcpu_run+0x196 ([kernel.kallsyms]) => ffffffffb22061a0 perf_guest_get_msrs+0x0 ([kernel.kallsyms]) 1587 CPU 3/KVM 13376/13384 [002] 7919.408804032: branches: ffffffffb22061a9 perf_guest_get_msrs+0x9 ([kernel.kallsyms]) => ffffffffb220cda0 intel_guest_get_msrs+0x0 ([kernel.kallsyms]) 1588 CPU 3/KVM 13376/13384 [002] 7919.408804039: branches: ffffffffc0f66109 vmx_vcpu_run+0x1d9 ([kernel.kallsyms]) => ffffffffc0f652c0 clear_atomic_switch_msr+0x0 ([kernel.kallsyms]) 1589 CPU 3/KVM 13376/13384 [002] 7919.408804040: branches: ffffffffc0f66119 vmx_vcpu_run+0x1e9 ([kernel.kallsyms]) => ffffffffc0f73f60 intel_pmu_lbr_is_enabled+0x0 ([kernel.kallsyms]) 1590 CPU 3/KVM 13376/13384 [002] 7919.408804042: branches: ffffffffc0f73f81 intel_pmu_lbr_is_enabled+0x21 ([kernel.kallsyms]) => ffffffffc10b68e0 kvm_find_cpuid_entry+0x0 ([kernel.kallsyms]) 1591 CPU 3/KVM 13376/13384 [002] 7919.408804045: branches: ffffffffc0f66454 vmx_vcpu_run+0x524 ([kernel.kallsyms]) => ffffffffc0f61ff0 vmx_update_hv_timer+0x0 ([kernel.kallsyms]) 1592 CPU 3/KVM 13376/13384 [002] 7919.408804057: branches: ffffffffc0f66142 vmx_vcpu_run+0x212 ([kernel.kallsyms]) => ffffffffc10af100 kvm_wait_lapic_expire+0x0 ([kernel.kallsyms]) 1593 CPU 3/KVM 13376/13384 [002] 7919.408804057: branches: ffffffffc0f66156 vmx_vcpu_run+0x226 ([kernel.kallsyms]) => ffffffffb2255c60 x86_virt_spec_ctrl+0x0 ([kernel.kallsyms]) 1594 CPU 3/KVM 13376/13384 [002] 7919.408804057: branches: ffffffffc0f66161 vmx_vcpu_run+0x231 ([kernel.kallsyms]) => ffffffffc0f8eb20 vmx_vcpu_enter_exit+0x0 ([kernel.kallsyms]) 1595 CPU 3/KVM 13376/13384 [002] 7919.408804057: branches: ffffffffc0f8eb44 vmx_vcpu_enter_exit+0x24 ([kernel.kallsyms]) => ffffffffb2353e10 rcu_note_context_switch+0x0 ([kernel.kallsyms]) 1596 CPU 3/KVM 13376/13384 [002] 7919.408804057: branches: ffffffffb2353e1c rcu_note_context_switch+0xc ([kernel.kallsyms]) => ffffffffb2353db0 rcu_qs+0x0 ([kernel.kallsyms]) 1597 CPU 3/KVM 13376/13384 [002] 7919.408804066: branches: ffffffffc0f8ebe0 vmx_vcpu_enter_exit+0xc0 ([kernel.kallsyms]) => ffffffffc0f8edc0 __vmx_vcpu_run+0x0 ([kernel.kallsyms]) 1598 CPU 3/KVM 13376/13384 [002] 7919.408804066: branches: ffffffffc0f8edd5 __vmx_vcpu_run+0x15 ([kernel.kallsyms]) => ffffffffc0f8eca0 vmx_update_host_rsp+0x0 ([kernel.kallsyms]) 1599 CPU 3/KVM 13376/13384 [002] 7919.408804066: branches: ffffffffc0f8ee1b __vmx_vcpu_run+0x5b ([kernel.kallsyms]) => ffffffffc0f8ed60 vmx_vmenter+0x0 ([kernel.kallsyms]) 1600 CPU 3/KVM 13376/13384 [002] 7919.408804162: branches: ffffffffc0f8ed62 vmx_vmenter+0x2 ([kernel.kallsyms]) => 0 [unknown] ([unknown]) 1601 VM:13376 VCPU:003 uname 3404/3404 [002] 7919.408804162: branches: 0 [unknown] ([unknown]) => 7f851c9b5a5c init_cacheinfo+0x3ac (/usr/lib/x86_64-linux-gnu/libc-2.31.so) 1602 VM:13376 VCPU:003 uname 3404/3404 [002] 7919.408804273: branches: 7f851cb7c0e4 _dl_init+0x74 (/usr/lib/x86_64-linux-gnu/ld-2.31.so) => 7f851cb7bf50 call_init.part.0+0x0 (/usr/lib/x86_64-linux-gnu/ld-2.31.so) 1603 VM:13376 VCPU:003 uname 3404/3404 [002] 7919.408804526: branches: 55e0c00136f0 _start+0x0 (/usr/bin/uname) => ffffffff83200ac0 asm_exc_page_fault+0x0 ([kernel.kallsyms]) 1604 VM:13376 VCPU:003 uname 3404/3404 [002] 7919.408804526: branches: ffffffff83200ac3 asm_exc_page_fault+0x3 ([kernel.kallsyms]) => ffffffff83201290 error_entry+0x0 ([kernel.kallsyms]) 1605 VM:13376 VCPU:003 uname 3404/3404 [002] 7919.408804534: branches: ffffffff832012fa error_entry+0x6a ([kernel.kallsyms]) => ffffffff830b59a0 sync_regs+0x0 ([kernel.kallsyms]) 1606 VM:13376 VCPU:003 uname 3404/3404 [002] 7919.408804631: branches: ffffffff83200ad9 asm_exc_page_fault+0x19 ([kernel.kallsyms]) => ffffffff830b8210 exc_page_fault+0x0 ([kernel.kallsyms]) 1607 VM:13376 VCPU:003 uname 3404/3404 [002] 7919.408804631: branches: ffffffff830b82a4 exc_page_fault+0x94 ([kernel.kallsyms]) => ffffffff830b80e0 __kvm_handle_async_pf+0x0 ([kernel.kallsyms]) 1608 VM:13376 VCPU:003 uname 3404/3404 [002] 7919.408804631: branches: ffffffff830b80ed __kvm_handle_async_pf+0xd ([kernel.kallsyms]) => ffffffff830b80c0 kvm_read_and_reset_apf_flags+0x0 ([kernel.kallsyms]) 1609 1610 1611Tracing Virtual Machines - Guest Code 1612------------------------------------- 1613 1614A common case for KVM test programs is that the test program acts as the 1615hypervisor, creating, running and destroying the virtual machine, and 1616providing the guest object code from its own object code. In this case, 1617the VM is not running an OS, but only the functions loaded into it by the 1618hypervisor test program, and conveniently, loaded at the same virtual 1619addresses. To support that, option "--guest-code" has been added to perf script 1620and perf kvm report. 1621 1622Here is an example tracing a test program from the kernel's KVM selftests: 1623 1624 # perf record --kcore -e intel_pt/cyc/ -- tools/testing/selftests/kselftest_install/kvm/tsc_msrs_test 1625 [ perf record: Woken up 1 times to write data ] 1626 [ perf record: Captured and wrote 0.280 MB perf.data ] 1627 # perf script --guest-code --itrace=bep --ns -F-period,+addr,+flags 1628 [SNIP] 1629 tsc_msrs_test 18436 [007] 10897.962087733: branches: call ffffffffc13b2ff5 __vmx_vcpu_run+0x15 (vmlinux) => ffffffffc13b2f50 vmx_update_host_rsp+0x0 (vmlinux) 1630 tsc_msrs_test 18436 [007] 10897.962087733: branches: return ffffffffc13b2f5d vmx_update_host_rsp+0xd (vmlinux) => ffffffffc13b2ffa __vmx_vcpu_run+0x1a (vmlinux) 1631 tsc_msrs_test 18436 [007] 10897.962087733: branches: call ffffffffc13b303b __vmx_vcpu_run+0x5b (vmlinux) => ffffffffc13b2f80 vmx_vmenter+0x0 (vmlinux) 1632 tsc_msrs_test 18436 [007] 10897.962087836: branches: vmentry ffffffffc13b2f82 vmx_vmenter+0x2 (vmlinux) => 0 [unknown] ([unknown]) 1633 [guest/18436] 18436 [007] 10897.962087836: branches: vmentry 0 [unknown] ([unknown]) => 402c81 guest_code+0x131 (/home/user/git/work/tools/testing/selftests/kselftest_install/kvm/tsc_msrs_test) 1634 [guest/18436] 18436 [007] 10897.962087836: branches: call 402c81 guest_code+0x131 (/home/user/git/work/tools/testing/selftests/kselftest_install/kvm/tsc_msrs_test) => 40dba0 ucall+0x0 (/home/user/git/work/tools/testing/selftests/kselftest_install/kvm/tsc_msrs_test) 1635 [guest/18436] 18436 [007] 10897.962088248: branches: vmexit 40dba0 ucall+0x0 (/home/user/git/work/tools/testing/selftests/kselftest_install/kvm/tsc_msrs_test) => 0 [unknown] ([unknown]) 1636 tsc_msrs_test 18436 [007] 10897.962088248: branches: vmexit 0 [unknown] ([unknown]) => ffffffffc13b2fa0 vmx_vmexit+0x0 (vmlinux) 1637 tsc_msrs_test 18436 [007] 10897.962088248: branches: jmp ffffffffc13b2fa0 vmx_vmexit+0x0 (vmlinux) => ffffffffc13b2fd2 vmx_vmexit+0x32 (vmlinux) 1638 tsc_msrs_test 18436 [007] 10897.962088256: branches: return ffffffffc13b2fd2 vmx_vmexit+0x32 (vmlinux) => ffffffffc13b3040 __vmx_vcpu_run+0x60 (vmlinux) 1639 tsc_msrs_test 18436 [007] 10897.962088270: branches: return ffffffffc13b30b6 __vmx_vcpu_run+0xd6 (vmlinux) => ffffffffc13b2f2e vmx_vcpu_enter_exit+0x4e (vmlinux) 1640 [SNIP] 1641 tsc_msrs_test 18436 [007] 10897.962089321: branches: call ffffffffc13b2ff5 __vmx_vcpu_run+0x15 (vmlinux) => ffffffffc13b2f50 vmx_update_host_rsp+0x0 (vmlinux) 1642 tsc_msrs_test 18436 [007] 10897.962089321: branches: return ffffffffc13b2f5d vmx_update_host_rsp+0xd (vmlinux) => ffffffffc13b2ffa __vmx_vcpu_run+0x1a (vmlinux) 1643 tsc_msrs_test 18436 [007] 10897.962089321: branches: call ffffffffc13b303b __vmx_vcpu_run+0x5b (vmlinux) => ffffffffc13b2f80 vmx_vmenter+0x0 (vmlinux) 1644 tsc_msrs_test 18436 [007] 10897.962089424: branches: vmentry ffffffffc13b2f82 vmx_vmenter+0x2 (vmlinux) => 0 [unknown] ([unknown]) 1645 [guest/18436] 18436 [007] 10897.962089424: branches: vmentry 0 [unknown] ([unknown]) => 40dba0 ucall+0x0 (/home/user/git/work/tools/testing/selftests/kselftest_install/kvm/tsc_msrs_test) 1646 [guest/18436] 18436 [007] 10897.962089701: branches: jmp 40dc1b ucall+0x7b (/home/user/git/work/tools/testing/selftests/kselftest_install/kvm/tsc_msrs_test) => 40dc39 ucall+0x99 (/home/user/git/work/tools/testing/selftests/kselftest_install/kvm/tsc_msrs_test) 1647 [guest/18436] 18436 [007] 10897.962089701: branches: jcc 40dc3c ucall+0x9c (/home/user/git/work/tools/testing/selftests/kselftest_install/kvm/tsc_msrs_test) => 40dc20 ucall+0x80 (/home/user/git/work/tools/testing/selftests/kselftest_install/kvm/tsc_msrs_test) 1648 [guest/18436] 18436 [007] 10897.962089701: branches: jcc 40dc3c ucall+0x9c (/home/user/git/work/tools/testing/selftests/kselftest_install/kvm/tsc_msrs_test) => 40dc20 ucall+0x80 (/home/user/git/work/tools/testing/selftests/kselftest_install/kvm/tsc_msrs_test) 1649 [guest/18436] 18436 [007] 10897.962089701: branches: jcc 40dc37 ucall+0x97 (/home/user/git/work/tools/testing/selftests/kselftest_install/kvm/tsc_msrs_test) => 40dc50 ucall+0xb0 (/home/user/git/work/tools/testing/selftests/kselftest_install/kvm/tsc_msrs_test) 1650 [guest/18436] 18436 [007] 10897.962089878: branches: vmexit 40dc55 ucall+0xb5 (/home/user/git/work/tools/testing/selftests/kselftest_install/kvm/tsc_msrs_test) => 0 [unknown] ([unknown]) 1651 tsc_msrs_test 18436 [007] 10897.962089878: branches: vmexit 0 [unknown] ([unknown]) => ffffffffc13b2fa0 vmx_vmexit+0x0 (vmlinux) 1652 tsc_msrs_test 18436 [007] 10897.962089878: branches: jmp ffffffffc13b2fa0 vmx_vmexit+0x0 (vmlinux) => ffffffffc13b2fd2 vmx_vmexit+0x32 (vmlinux) 1653 tsc_msrs_test 18436 [007] 10897.962089887: branches: return ffffffffc13b2fd2 vmx_vmexit+0x32 (vmlinux) => ffffffffc13b3040 __vmx_vcpu_run+0x60 (vmlinux) 1654 tsc_msrs_test 18436 [007] 10897.962089901: branches: return ffffffffc13b30b6 __vmx_vcpu_run+0xd6 (vmlinux) => ffffffffc13b2f2e vmx_vcpu_enter_exit+0x4e (vmlinux) 1655 [SNIP] 1656 1657 # perf kvm --guest-code --guest --host report -i perf.data --stdio | head -20 1658 1659 # To display the perf.data header info, please use --header/--header-only options. 1660 # 1661 # 1662 # Total Lost Samples: 0 1663 # 1664 # Samples: 12 of event 'instructions' 1665 # Event count (approx.): 2274583 1666 # 1667 # Children Self Command Shared Object Symbol 1668 # ........ ........ ............. .................... ........................................... 1669 # 1670 54.70% 0.00% tsc_msrs_test [kernel.vmlinux] [k] entry_SYSCALL_64_after_hwframe 1671 | 1672 ---entry_SYSCALL_64_after_hwframe 1673 do_syscall_64 1674 | 1675 |--29.44%--syscall_exit_to_user_mode 1676 | exit_to_user_mode_prepare 1677 | task_work_run 1678 | __fput 1679 1680 1681Event Trace 1682----------- 1683 1684Event Trace records information about asynchronous events, for example interrupts, 1685faults, VM exits and entries. The information is recorded in CFE and EVD packets, 1686and also the Interrupt Flag is recorded on the MODE.Exec packet. The CFE packet 1687contains a type field to identify one of the following: 1688 1689 1 INTR interrupt, fault, exception, NMI 1690 2 IRET interrupt return 1691 3 SMI system management interrupt 1692 4 RSM resume from system management mode 1693 5 SIPI startup interprocessor interrupt 1694 6 INIT INIT signal 1695 7 VMENTRY VM-Entry 1696 8 VMEXIT VM-Entry 1697 9 VMEXIT_INTR VM-Exit due to interrupt 1698 10 SHUTDOWN Shutdown 1699 1700For more details, refer to the Intel 64 and IA-32 Architectures Software 1701Developer Manuals (version 076 or later). 1702 1703The capability to do Event Trace is indicated by the 1704/sys/bus/event_source/devices/intel_pt/caps/event_trace file. 1705 1706Event trace is selected for recording using the "event" config term. e.g. 1707 1708 perf record -e intel_pt/event/u uname 1709 1710Event trace events are output using the --itrace I option. e.g. 1711 1712 perf script --itrace=Ie 1713 1714perf script displays events containing CFE type, vector and event data, 1715in the form: 1716 1717 evt: hw int (t) cfe: INTR IP: 1 vector: 3 PFA: 0x8877665544332211 1718 1719The IP flag indicates if the event binds to an IP, which includes any case where 1720flow control packet generation is enabled, as well as when CFE packet IP bit is 1721set. 1722 1723perf script displays events containing changes to the Interrupt Flag in the form: 1724 1725 iflag: t IFLAG: 1->0 via branch 1726 1727where "via branch" indicates a branch (interrupt or return from interrupt) and 1728"non branch" indicates an instruction such as CFI, STI or POPF). 1729 1730In addition, the current state of the interrupt flag is indicated by the presence 1731or absence of the "D" (interrupt disabled) perf script flag. If the interrupt 1732flag is changed, then the "t" flag is also included i.e. 1733 1734 no flag, interrupts enabled IF=1 1735 t interrupts become disabled IF=1 -> IF=0 1736 D interrupts are disabled IF=0 1737 Dt interrupts become enabled IF=0 -> IF=1 1738 1739The intel-pt-events.py script illustrates how to access Event Trace information 1740using a Python script. 1741 1742 1743TNT Disable 1744----------- 1745 1746TNT packets are disabled using the "notnt" config term. e.g. 1747 1748 perf record -e intel_pt/notnt/u uname 1749 1750In that case the --itrace q option is forced because walking executable code 1751to reconstruct the control flow is not possible. 1752 1753 1754Emulated PTWRITE 1755---------------- 1756 1757Later perf tools support a method to emulate the ptwrite instruction, which 1758can be useful if hardware does not support the ptwrite instruction. 1759 1760Instead of using the ptwrite instruction, a function is used which produces 1761a trace that encodes the payload data into TNT packets. Here is an example 1762of the function: 1763 1764 #include <stdint.h> 1765 1766 void perf_emulate_ptwrite(uint64_t x) 1767 __attribute__((externally_visible, noipa, no_instrument_function, naked)); 1768 1769 #define PERF_EMULATE_PTWRITE_8_BITS \ 1770 "1: shl %rax\n" \ 1771 " jc 1f\n" \ 1772 "1: shl %rax\n" \ 1773 " jc 1f\n" \ 1774 "1: shl %rax\n" \ 1775 " jc 1f\n" \ 1776 "1: shl %rax\n" \ 1777 " jc 1f\n" \ 1778 "1: shl %rax\n" \ 1779 " jc 1f\n" \ 1780 "1: shl %rax\n" \ 1781 " jc 1f\n" \ 1782 "1: shl %rax\n" \ 1783 " jc 1f\n" \ 1784 "1: shl %rax\n" \ 1785 " jc 1f\n" 1786 1787 /* Undefined instruction */ 1788 #define PERF_EMULATE_PTWRITE_UD2 ".byte 0x0f, 0x0b\n" 1789 1790 #define PERF_EMULATE_PTWRITE_MAGIC PERF_EMULATE_PTWRITE_UD2 ".ascii \"perf,ptwrite \"\n" 1791 1792 void perf_emulate_ptwrite(uint64_t x __attribute__ ((__unused__))) 1793 { 1794 /* Assumes SysV ABI : x passed in rdi */ 1795 __asm__ volatile ( 1796 "jmp 1f\n" 1797 PERF_EMULATE_PTWRITE_MAGIC 1798 "1: mov %rdi, %rax\n" 1799 PERF_EMULATE_PTWRITE_8_BITS 1800 PERF_EMULATE_PTWRITE_8_BITS 1801 PERF_EMULATE_PTWRITE_8_BITS 1802 PERF_EMULATE_PTWRITE_8_BITS 1803 PERF_EMULATE_PTWRITE_8_BITS 1804 PERF_EMULATE_PTWRITE_8_BITS 1805 PERF_EMULATE_PTWRITE_8_BITS 1806 PERF_EMULATE_PTWRITE_8_BITS 1807 "1: ret\n" 1808 ); 1809 } 1810 1811For example, a test program with the function above: 1812 1813 #include <stdio.h> 1814 #include <stdint.h> 1815 #include <stdlib.h> 1816 1817 #include "perf_emulate_ptwrite.h" 1818 1819 int main(int argc, char *argv[]) 1820 { 1821 uint64_t x = 0; 1822 1823 if (argc > 1) 1824 x = strtoull(argv[1], NULL, 0); 1825 perf_emulate_ptwrite(x); 1826 return 0; 1827 } 1828 1829Can be compiled and traced: 1830 1831 $ gcc -Wall -Wextra -O3 -g -o eg_ptw eg_ptw.c 1832 $ perf record -e intel_pt//u ./eg_ptw 0x1234567890abcdef 1833 [ perf record: Woken up 1 times to write data ] 1834 [ perf record: Captured and wrote 0.017 MB perf.data ] 1835 $ perf script --itrace=ew 1836 eg_ptw 19875 [007] 8061.235912: ptwrite: IP: 0 payload: 0x1234567890abcdef 55701249a196 perf_emulate_ptwrite+0x16 (/home/user/eg_ptw) 1837 $ 1838 1839 1840Pipe mode 1841--------- 1842Pipe mode is a problem for Intel PT and possibly other auxtrace users. 1843It's not recommended to use a pipe as data output with Intel PT because 1844of the following reason. 1845 1846Essentially the auxtrace buffers do not behave like the regular perf 1847event buffers. That is because the head and tail are updated by 1848software, but in the auxtrace case the data is written by hardware. 1849So the head and tail do not get updated as data is written. 1850 1851In the Intel PT case, the head and tail are updated only when the trace 1852is disabled by software, for example: 1853 - full-trace, system wide : when buffer passes watermark 1854 - full-trace, not system-wide : when buffer passes watermark or 1855 context switches 1856 - snapshot mode : as above but also when a snapshot is made 1857 - sample mode : as above but also when a sample is made 1858 1859That means finished-round ordering doesn't work. An auxtrace buffer 1860can turn up that has data that extends back in time, possibly to the 1861very beginning of tracing. 1862 1863For a perf.data file, that problem is solved by going through the trace 1864and queuing up the auxtrace buffers in advance. 1865 1866For pipe mode, the order of events and timestamps can presumably 1867be messed up. 1868 1869 1870EXAMPLE 1871------- 1872 1873Examples can be found on perf wiki page "Perf tools support for Intel® Processor Trace": 1874 1875https://perf.wiki.kernel.org/index.php/Perf_tools_support_for_Intel%C2%AE_Processor_Trace 1876 1877 1878SEE ALSO 1879-------- 1880 1881linkperf:perf-record[1], linkperf:perf-script[1], linkperf:perf-report[1], 1882linkperf:perf-inject[1] 1883