Searched refs:cik (Results 1 – 6 of 6) sorted by relevance
2322 u32 *tile = rdev->config.cik.tile_mode_array; in cik_tiling_mode_table_init()2323 u32 *macrotile = rdev->config.cik.macrotile_mode_array; in cik_tiling_mode_table_init()2325 ARRAY_SIZE(rdev->config.cik.tile_mode_array); in cik_tiling_mode_table_init()2327 ARRAY_SIZE(rdev->config.cik.macrotile_mode_array); in cik_tiling_mode_table_init()2330 u32 num_rbs = rdev->config.cik.max_backends_per_se * in cik_tiling_mode_table_init()2331 rdev->config.cik.max_shader_engines; in cik_tiling_mode_table_init()2333 switch (rdev->config.cik.mem_row_size_in_kb) { in cik_tiling_mode_table_init()2346 num_pipe_configs = rdev->config.cik.max_tile_pipes; in cik_tiling_mode_table_init()3129 rdev->config.cik.backend_enable_mask = enabled_rbs; in cik_setup_rb()3178 rdev->config.cik.max_shader_engines = 2; in cik_gpu_init()[all …]
298 *value = rdev->config.cik.tile_config; in radeon_info_ioctl()352 *value = rdev->config.cik.max_backends_per_se * in radeon_info_ioctl()353 rdev->config.cik.max_shader_engines; in radeon_info_ioctl()372 *value = rdev->config.cik.max_tile_pipes; in radeon_info_ioctl()392 *value = rdev->config.cik.backend_map; in radeon_info_ioctl()421 *value = rdev->config.cik.max_cu_per_sh; in radeon_info_ioctl()447 *value = rdev->config.cik.max_shader_engines; in radeon_info_ioctl()459 *value = rdev->config.cik.max_sh_per_se; in radeon_info_ioctl()494 value = rdev->config.cik.tile_mode_array; in radeon_info_ioctl()506 value = rdev->config.cik.macrotile_mode_array; in radeon_info_ioctl()[all …]
47 radeon_prime.o cik.o \
1290 num_banks = (rdev->config.cik.macrotile_mode_array[index] >> 6) & 0x3; in dce4_crtc_do_set_base()1346 u32 pipe_config = (rdev->config.cik.tile_mode_array[10] >> 6) & 0x1f; in dce4_crtc_do_set_base()
749 struct cik_irq_stat_regs cik; member2193 struct cik_asic cik; member
75 amdgpu-$(CONFIG_DRM_AMDGPU_CIK)+= cik.o cik_ih.o \