Home
last modified time | relevance | path

Searched refs:chunk_hdl_adjust_cur0 (Results 1 – 14 of 14) sorted by relevance

/linux/drivers/gpu/drm/amd/display/dc/dml2/dml21/inc/
H A Ddml_top_dchub_registers.h44 uint32_t chunk_hdl_adjust_cur0; member
/linux/drivers/gpu/drm/amd/display/dc/dml/
H A Ddisplay_rq_dlg_helpers.c299 dlg_regs->chunk_hdl_adjust_cur0); in print__dlg_regs_st()
H A Ddisplay_mode_structs.h657 unsigned int chunk_hdl_adjust_cur0; member
H A Ddml1_display_rq_dlg_calc.c1731 disp_dlg_regs->chunk_hdl_adjust_cur0 = 3; in dml1_rq_dlg_get_dlg_params()
/linux/drivers/gpu/drm/amd/display/dc/dml2/dml21/
H A Ddml21_utils.c218 out->dlg_regs.chunk_hdl_adjust_cur0 = disp_dlg_regs->chunk_hdl_adjust_cur0; in dml21_update_pipe_ctx_dchub_regs()
/linux/drivers/gpu/drm/amd/display/dc/dml/dcn32/
H A Ddisplay_rq_dlg_calc_32.c525 dlg_regs->chunk_hdl_adjust_cur0 = 3; in dml32_rq_dlg_get_dlg_reg()
/linux/drivers/gpu/drm/amd/display/dc/dml2/
H A Ddml_display_rq_dlg_calc.c487 disp_dlg_regs->chunk_hdl_adjust_cur0 = 3; in dml_rq_dlg_get_dlg_reg()
H A Ddml2_translation_helper.c1474 out->dlg_regs.chunk_hdl_adjust_cur0 = disp_dlg_regs->chunk_hdl_adjust_cur0; in dml2_update_pipe_ctx_dchub_regs()
H A Ddisplay_mode_util.c291 dml_print("DML: chunk_hdl_adjust_cur0 = 0x%x\n", dlg_regs->chunk_hdl_adjust_cur0); in dml_print_dlg_regs_st()
H A Ddisplay_mode_core_structs.h1912 dml_uint_t chunk_hdl_adjust_cur0; member
/linux/drivers/gpu/drm/amd/display/dc/dml/dcn21/
H A Ddisplay_rq_dlg_calc_21.c1593 disp_dlg_regs->chunk_hdl_adjust_cur0 = 3; in dml_rq_dlg_get_dlg_params()
/linux/drivers/gpu/drm/amd/display/dc/dml/dcn20/
H A Ddisplay_rq_dlg_calc_20.c1485 disp_dlg_regs->chunk_hdl_adjust_cur0 = 3; in dml20_rq_dlg_get_dlg_params()
H A Ddisplay_rq_dlg_calc_20v2.c1486 disp_dlg_regs->chunk_hdl_adjust_cur0 = 3; in dml20v2_rq_dlg_get_dlg_params()
/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn10/
H A Ddcn10_hwseq.c260 …dlg_regs->refcyc_per_line_delivery_c, dlg_regs->chunk_hdl_adjust_cur0, dlg_regs->dst_y_offset_cur1, in dcn10_log_hubp_states()