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Searched refs:channel_writel (Results 1 – 6 of 6) sorted by relevance

/linux/drivers/dma/dw/
H A Didma32.c137 channel_writel(dwc, CFG_LO, cfglo); in idma32_initialize_chan_xbar()
138 channel_writel(dwc, CFG_HI, cfghi); in idma32_initialize_chan_xbar()
157 channel_writel(dwc, CFG_LO, cfglo); in idma32_initialize_chan_generic()
158 channel_writel(dwc, CFG_HI, cfghi); in idma32_initialize_chan_generic()
168 channel_writel(dwc, CFG_LO, cfglo | DWC_CFGL_CH_SUSP); in idma32_suspend_chan()
178 channel_writel(dwc, CFG_LO, cfglo & ~DWC_CFGL_CH_SUSP); in idma32_resume_chan()
H A Ddw.c28 channel_writel(dwc, CFG_LO, cfglo); in dw_dma_initialize_chan()
29 channel_writel(dwc, CFG_HI, cfghi); in dw_dma_initialize_chan()
36 channel_writel(dwc, CFG_LO, cfglo | DWC_CFGL_CH_SUSP); in dw_dma_suspend_chan()
43 channel_writel(dwc, CFG_LO, cfglo & ~DWC_CFGL_CH_SUSP); in dw_dma_resume_chan()
H A Dcore.c161 channel_writel(dwc, SAR, lli_read(desc, sar)); in dwc_do_single_block()
162 channel_writel(dwc, DAR, lli_read(desc, dar)); in dwc_do_single_block()
163 channel_writel(dwc, CTL_LO, ctllo); in dwc_do_single_block()
164 channel_writel(dwc, CTL_HI, lli_read(desc, ctlhi)); in dwc_do_single_block()
211 channel_writel(dwc, LLP, first->txd.phys | lms); in dwc_dostart()
212 channel_writel(dwc, CTL_LO, DWC_CTLL_LLP_D_EN | DWC_CTLL_LLP_S_EN); in dwc_dostart()
213 channel_writel(dwc, CTL_HI, 0); in dwc_dostart()
H A Dregs.h305 #define channel_writel(dwc, name, val) \ macro
/linux/drivers/dma/
H A Dat_hdmac.c300 #define channel_writel(atchan, name, val) \ macro
573 channel_writel(atchan, SADDR, 0); in atc_dostart()
574 channel_writel(atchan, DADDR, 0); in atc_dostart()
575 channel_writel(atchan, CTRLA, 0); in atc_dostart()
576 channel_writel(atchan, CTRLB, 0); in atc_dostart()
577 channel_writel(atchan, DSCR, desc->sg[0].lli_phys); in atc_dostart()
578 channel_writel(atchan, SPIP, in atc_dostart()
581 channel_writel(atchan, DPIP, in atc_dostart()
1756 channel_writel(atchan, CFG, cfg); in atc_alloc_chan_resources()
2212 channel_writel(atchan, SADDR, 0); in atc_resume_cyclic()
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H A Didma64.h164 #define channel_writel(idma64c, reg, value) \ macro