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Searched refs:chan (Results 1 – 25 of 1302) sorted by relevance

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/linux/drivers/dma/
H A Dfsldma.c39 #define chan_dbg(chan, fmt, arg...) \ argument
40 dev_dbg(chan->dev, "%s: " fmt, chan->name, ##arg)
41 #define chan_err(chan, fmt, arg...) \ argument
42 dev_err(chan->dev, "%s: " fmt, chan->name, ##arg)
50 static void set_sr(struct fsldma_chan *chan, u32 val) in set_sr() argument
52 FSL_DMA_OUT(chan, &chan->regs->sr, val, 32); in set_sr()
55 static u32 get_sr(struct fsldma_chan *chan) in get_sr() argument
57 return FSL_DMA_IN(chan, &chan->regs->sr, 32); in get_sr()
60 static void set_mr(struct fsldma_chan *chan, u32 val) in set_mr() argument
62 FSL_DMA_OUT(chan, &chan->regs->mr, val, 32); in set_mr()
[all …]
H A Ddmaengine.c88 struct dma_chan *chan; in dmaengine_dbg_summary_show() local
90 list_for_each_entry(chan, &dma_dev->channels, device_node) { in dmaengine_dbg_summary_show()
91 if (chan->client_count) { in dmaengine_dbg_summary_show()
92 seq_printf(s, " %-13s| %s", dma_chan_name(chan), in dmaengine_dbg_summary_show()
93 chan->dbg_client_name ?: "in-use"); in dmaengine_dbg_summary_show()
95 if (chan->router) in dmaengine_dbg_summary_show()
97 dev_name(chan->router->dev)); in dmaengine_dbg_summary_show()
161 return chan_dev->chan; in dev_to_dma_chan()
167 struct dma_chan *chan; in memcpy_count_show() local
173 chan = dev_to_dma_chan(dev); in memcpy_count_show()
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/linux/arch/um/drivers/
H A Dchan_kern.c90 static int open_one_chan(struct chan *chan) in open_one_chan() argument
94 if (chan->opened) in open_one_chan()
97 if (chan->ops->open == NULL) in open_one_chan()
99 else fd = (*chan->ops->open)(chan->input, chan->output, chan->primary, in open_one_chan()
100 chan->data, &chan->dev); in open_one_chan()
108 chan->fd_in = fd; in open_one_chan()
109 chan->fd_out = fd; in open_one_chan()
122 if (chan->output && need_output_blocking()) { in open_one_chan()
123 err = os_dup_file(chan->fd_out); in open_one_chan()
127 chan->fd_out = err; in open_one_chan()
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/linux/net/bluetooth/
H A Dl2cap_core.c54 static int l2cap_build_conf_req(struct l2cap_chan *chan, void *data, size_t data_size);
55 static void l2cap_send_disconn_req(struct l2cap_chan *chan, int err);
57 static void l2cap_tx(struct l2cap_chan *chan, struct l2cap_ctrl *control,
179 int l2cap_add_psm(struct l2cap_chan *chan, bdaddr_t *src, __le16 psm) in l2cap_add_psm() argument
185 if (psm && __l2cap_global_chan_by_addr(psm, src, chan->src_type)) { in l2cap_add_psm()
191 chan->psm = psm; in l2cap_add_psm()
192 chan->sport = psm; in l2cap_add_psm()
197 if (chan->src_type == BDADDR_BREDR) { in l2cap_add_psm()
210 chan->src_type)) { in l2cap_add_psm()
211 chan->psm = cpu_to_le16(p); in l2cap_add_psm()
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/linux/sound/soc/qcom/
H A Dlpass-lpaif-reg.h102 #define LPAIF_IRQ_PER(chan) (1 << (LPAIF_IRQ_BITSTRIDE * (chan))) argument
103 #define LPAIF_IRQ_XRUN(chan) (2 << (LPAIF_IRQ_BITSTRIDE * (chan))) argument
104 #define LPAIF_IRQ_ERR(chan) (4 << (LPAIF_IRQ_BITSTRIDE * (chan))) argument
106 #define LPAIF_IRQ_ALL(chan) (7 << (LPAIF_IRQ_BITSTRIDE * (chan))) argument
107 #define LPAIF_IRQ_HDMI_REQ_ON_PRELOAD(chan) (1 << (14 + chan)) argument
108 #define LPAIF_IRQ_HDMI_SDEEP_AUD_DIS(chan) (1 << (24 + chan)) argument
112 #define LPAIF_HDMI_RDMA_REG_ADDR(v, addr, chan) \ argument
113 (v->hdmi_rdma_reg_base + (addr) + v->hdmi_rdma_reg_stride * (chan))
117 #define LPAIF_HDMI_RDMACTL_REG(v, chan) LPAIF_HDMI_RDMA_REG_ADDR(v, 0x00, (chan)) argument
118 #define LPAIF_HDMI_RDMABASE_REG(v, chan) LPAIF_HDMI_RDMA_REG_ADDR(v, 0x04, (chan)) argument
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/linux/drivers/video/fbdev/savage/
H A Dsavagefb-i2c.c47 struct savagefb_i2c_chan *chan = data; in savage4_gpio_setscl() local
50 r = readl(chan->ioaddr + chan->reg); in savage4_gpio_setscl()
55 writel(r, chan->ioaddr + chan->reg); in savage4_gpio_setscl()
56 readl(chan->ioaddr + chan->reg); /* flush posted write */ in savage4_gpio_setscl()
61 struct savagefb_i2c_chan *chan = data; in savage4_gpio_setsda() local
64 r = readl(chan->ioaddr + chan->reg); in savage4_gpio_setsda()
69 writel(r, chan->ioaddr + chan->reg); in savage4_gpio_setsda()
70 readl(chan->ioaddr + chan->reg); /* flush posted write */ in savage4_gpio_setsda()
75 struct savagefb_i2c_chan *chan = data; in savage4_gpio_getscl() local
77 return (0 != (readl(chan->ioaddr + chan->reg) & SAVAGE4_I2C_SCL_IN)); in savage4_gpio_getscl()
[all …]
/linux/drivers/gpu/drm/nouveau/nvkm/engine/fifo/
H A Dchan.c41 nvkm_chan_cctx_bind(struct nvkm_chan *chan, struct nvkm_engn *engn, struct nvkm_cctx *cctx) in nvkm_chan_cctx_bind() argument
43 struct nvkm_cgrp *cgrp = chan->cgrp; in nvkm_chan_cctx_bind()
50 CHAN_TRACE(chan, "%sbind cctx %d[%s]", cctx ? "" : "un", engn->id, engine->subdev.name); in nvkm_chan_cctx_bind()
58 nvkm_chan_block(chan); in nvkm_chan_cctx_bind()
59 nvkm_chan_preempt(chan, true); in nvkm_chan_cctx_bind()
62 engn->func->bind(engn, cctx, chan); in nvkm_chan_cctx_bind()
68 nvkm_chan_allow(chan); in nvkm_chan_cctx_bind()
72 nvkm_chan_cctx_put(struct nvkm_chan *chan, struct nvkm_cctx **pcctx) in nvkm_chan_cctx_put() argument
79 if (refcount_dec_and_mutex_lock(&cctx->refs, &chan->cgrp->mutex)) { in nvkm_chan_cctx_put()
80 CHAN_TRACE(chan, "dtor cctx %d[%s]", engn->id, engn->engine->subdev.name); in nvkm_chan_cctx_put()
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/linux/drivers/dma/xilinx/
H A Dxilinx_dma.c457 void (*start_transfer)(struct xilinx_dma_chan *chan);
458 int (*stop_transfer)(struct xilinx_dma_chan *chan);
513 struct xilinx_dma_chan *chan[XILINX_MCDMA_MAX_CHANS_PER_DEVICE]; member
530 #define to_xilinx_chan(chan) \ argument
531 container_of(chan, struct xilinx_dma_chan, common)
534 #define xilinx_dma_poll_timeout(chan, reg, val, cond, delay_us, timeout_us) \ argument
535 readl_poll_timeout_atomic(chan->xdev->regs + chan->ctrl_offset + reg, \
539 static inline u32 dma_read(struct xilinx_dma_chan *chan, u32 reg) in dma_read() argument
541 return ioread32(chan->xdev->regs + reg); in dma_read()
544 static inline void dma_write(struct xilinx_dma_chan *chan, u32 reg, u32 value) in dma_write() argument
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H A Dzynqmp_dma.c25 #define ZYNQMP_DMA_ISR (chan->irq_offset + 0x100)
26 #define ZYNQMP_DMA_IMR (chan->irq_offset + 0x104)
27 #define ZYNQMP_DMA_IER (chan->irq_offset + 0x108)
28 #define ZYNQMP_DMA_IDS (chan->irq_offset + 0x10c)
141 #define ZYNQMP_DMA_DESC_SIZE(chan) (chan->desc_size) argument
143 #define to_chan(chan) container_of(chan, struct zynqmp_dma_chan, \ argument
256 struct zynqmp_dma_chan *chan; member
269 static inline void zynqmp_dma_writeq(struct zynqmp_dma_chan *chan, u32 reg, in zynqmp_dma_writeq() argument
272 lo_hi_writeq(value, chan->regs + reg); in zynqmp_dma_writeq()
280 static void zynqmp_dma_update_desc_to_ctrlr(struct zynqmp_dma_chan *chan, in zynqmp_dma_update_desc_to_ctrlr() argument
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/linux/drivers/gpu/drm/nouveau/
H A Dnouveau_chan.c44 nouveau_channel_kill(struct nouveau_channel *chan) in nouveau_channel_kill() argument
46 atomic_set(&chan->killed, 1); in nouveau_channel_kill()
47 if (chan->fence) in nouveau_channel_kill()
48 nouveau_fence_context_kill(chan->fence, -ENODEV); in nouveau_channel_kill()
54 struct nouveau_channel *chan = container_of(event, typeof(*chan), kill); in nouveau_channel_killed() local
55 struct nouveau_cli *cli = chan->cli; in nouveau_channel_killed()
57 NV_PRINTK(warn, cli, "channel %d killed!\n", chan->chid); in nouveau_channel_killed()
59 if (unlikely(!atomic_read(&chan->killed))) in nouveau_channel_killed()
60 nouveau_channel_kill(chan); in nouveau_channel_killed()
66 nouveau_channel_idle(struct nouveau_channel *chan) in nouveau_channel_idle() argument
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/linux/arch/sh/drivers/dma/
H A Ddma-sh.c39 static unsigned long dma_find_base(unsigned int chan) in dma_find_base() argument
44 if (chan >= SH_DMAC_NR_MD_CH) in dma_find_base()
51 static unsigned long dma_base_addr(unsigned int chan) in dma_base_addr() argument
53 unsigned long base = dma_find_base(chan); in dma_base_addr()
55 chan = (chan % SH_DMAC_NR_MD_CH) * SH_DMAC_CH_SZ; in dma_base_addr()
58 if (chan >= DMAOR) in dma_base_addr()
61 return base + chan; in dma_base_addr()
65 static inline unsigned int get_dmte_irq(unsigned int chan) in get_dmte_irq() argument
67 return chan >= 6 ? DMTE6_IRQ : DMTE0_IRQ; in get_dmte_irq()
87 static inline unsigned int get_dmte_irq(unsigned int chan) in get_dmte_irq() argument
[all …]
/linux/drivers/video/fbdev/i810/
H A Di810-i2c.c44 struct i810fb_i2c_chan *chan = data; in i810i2c_setscl() local
45 struct i810fb_par *par = chan->par; in i810i2c_setscl()
49 i810_writel(mmio, chan->ddc_base, SCL_DIR_MASK | SCL_VAL_MASK); in i810i2c_setscl()
51 i810_writel(mmio, chan->ddc_base, SCL_DIR | SCL_DIR_MASK | SCL_VAL_MASK); in i810i2c_setscl()
52 i810_readl(mmio, chan->ddc_base); /* flush posted write */ in i810i2c_setscl()
57 struct i810fb_i2c_chan *chan = data; in i810i2c_setsda() local
58 struct i810fb_par *par = chan->par; in i810i2c_setsda()
62 i810_writel(mmio, chan->ddc_base, SDA_DIR_MASK | SDA_VAL_MASK); in i810i2c_setsda()
64 i810_writel(mmio, chan->ddc_base, SDA_DIR | SDA_DIR_MASK | SDA_VAL_MASK); in i810i2c_setsda()
65 i810_readl(mmio, chan->ddc_base); /* flush posted write */ in i810i2c_setsda()
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/linux/arch/mips/include/asm/mach-au1x00/
H A Dau1000_dma.h155 struct dma_chan *chan = get_dma_chan(dmanr); in enable_dma_buffer0() local
157 if (!chan) in enable_dma_buffer0()
159 __raw_writel(DMA_BE0, chan->io + DMA_MODE_SET); in enable_dma_buffer0()
164 struct dma_chan *chan = get_dma_chan(dmanr); in enable_dma_buffer1() local
166 if (!chan) in enable_dma_buffer1()
168 __raw_writel(DMA_BE1, chan->io + DMA_MODE_SET); in enable_dma_buffer1()
172 struct dma_chan *chan = get_dma_chan(dmanr); in enable_dma_buffers() local
174 if (!chan) in enable_dma_buffers()
176 __raw_writel(DMA_BE0 | DMA_BE1, chan->io + DMA_MODE_SET); in enable_dma_buffers()
181 struct dma_chan *chan = get_dma_chan(dmanr); in start_dma() local
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/linux/drivers/gpu/drm/gma500/
H A Doaktrail_lvds_i2c.c63 #define LPC_READ_REG(chan, r) inl((chan)->reg + (r)) argument
64 #define LPC_WRITE_REG(chan, r, val) outl((val), (chan)->reg + (r)) argument
68 struct gma_i2c_chan *chan = data; in get_clock() local
71 val = LPC_READ_REG(chan, RGIO); in get_clock()
73 LPC_WRITE_REG(chan, RGIO, val); in get_clock()
74 LPC_READ_REG(chan, RGLVL); in get_clock()
75 val = (LPC_READ_REG(chan, RGLVL) & GPIO_CLOCK) ? 1 : 0; in get_clock()
82 struct gma_i2c_chan *chan = data; in get_data() local
85 val = LPC_READ_REG(chan, RGIO); in get_data()
87 LPC_WRITE_REG(chan, RGIO, val); in get_data()
[all …]
H A Dintel_i2c.c25 struct gma_i2c_chan *chan = data; in get_clock() local
26 struct drm_device *dev = chan->drm_dev; in get_clock()
29 val = REG_READ(chan->reg); in get_clock()
35 struct gma_i2c_chan *chan = data; in get_data() local
36 struct drm_device *dev = chan->drm_dev; in get_data()
39 val = REG_READ(chan->reg); in get_data()
45 struct gma_i2c_chan *chan = data; in set_clock() local
46 struct drm_device *dev = chan->drm_dev; in set_clock()
51 REG_READ(chan->reg) & (GPIO_DATA_PULLUP_DISABLE | in set_clock()
59 REG_WRITE(chan->reg, reserved | clock_bits); in set_clock()
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/linux/drivers/gpu/drm/nouveau/nvif/
H A Dchan.c10 struct nvif_chan *chan = container_of(push, typeof(*chan), push); in nvif_chan_gpfifo_push_kick() local
11 u32 put = push->bgn - (u32 *)chan->push.mem.object.map.ptr; in nvif_chan_gpfifo_push_kick()
14 if (chan->func->gpfifo.post) { in nvif_chan_gpfifo_push_kick()
15 if (push->end - push->cur < chan->func->gpfifo.post_size) in nvif_chan_gpfifo_push_kick()
16 push->end = push->cur + chan->func->gpfifo.post_size; in nvif_chan_gpfifo_push_kick()
18 WARN_ON(nvif_chan_gpfifo_post(chan)); in nvif_chan_gpfifo_push_kick()
23 chan->func->gpfifo.push(chan, true, chan->push.addr + (put << 2), cnt << 2, false); in nvif_chan_gpfifo_push_kick()
24 chan->func->gpfifo.kick(chan); in nvif_chan_gpfifo_push_kick()
30 struct nvif_chan *chan = container_of(push, typeof(*chan), push); in nvif_chan_gpfifo_push_wait() local
32 return nvif_chan_gpfifo_wait(chan, 1, push_nr); in nvif_chan_gpfifo_push_wait()
[all …]
/linux/drivers/gpu/drm/nouveau/nvkm/engine/gr/
H A Dnv25.c25 struct nv20_gr_chan *chan; in nv25_gr_chan_new() local
28 if (!(chan = kzalloc_obj(*chan))) in nv25_gr_chan_new()
30 nvkm_object_ctor(&nv25_gr_chan, oclass, &chan->object); in nv25_gr_chan_new()
31 chan->gr = gr; in nv25_gr_chan_new()
32 chan->chid = fifoch->id; in nv25_gr_chan_new()
33 *pobject = &chan->object; in nv25_gr_chan_new()
37 &chan->inst); in nv25_gr_chan_new()
41 nvkm_kmap(chan->inst); in nv25_gr_chan_new()
42 nvkm_wo32(chan->inst, 0x0028, 0x00000001 | (chan->chid << 24)); in nv25_gr_chan_new()
43 nvkm_wo32(chan->inst, 0x035c, 0xffff0000); in nv25_gr_chan_new()
[all …]
H A Dnv34.c25 struct nv20_gr_chan *chan; in nv34_gr_chan_new() local
28 if (!(chan = kzalloc_obj(*chan))) in nv34_gr_chan_new()
30 nvkm_object_ctor(&nv34_gr_chan, oclass, &chan->object); in nv34_gr_chan_new()
31 chan->gr = gr; in nv34_gr_chan_new()
32 chan->chid = fifoch->id; in nv34_gr_chan_new()
33 *pobject = &chan->object; in nv34_gr_chan_new()
37 &chan->inst); in nv34_gr_chan_new()
41 nvkm_kmap(chan->inst); in nv34_gr_chan_new()
42 nvkm_wo32(chan->inst, 0x0028, 0x00000001 | (chan->chid << 24)); in nv34_gr_chan_new()
43 nvkm_wo32(chan->inst, 0x040c, 0x01000101); in nv34_gr_chan_new()
[all …]
H A Dnv35.c25 struct nv20_gr_chan *chan; in nv35_gr_chan_new() local
28 if (!(chan = kzalloc_obj(*chan))) in nv35_gr_chan_new()
30 nvkm_object_ctor(&nv35_gr_chan, oclass, &chan->object); in nv35_gr_chan_new()
31 chan->gr = gr; in nv35_gr_chan_new()
32 chan->chid = fifoch->id; in nv35_gr_chan_new()
33 *pobject = &chan->object; in nv35_gr_chan_new()
37 &chan->inst); in nv35_gr_chan_new()
41 nvkm_kmap(chan->inst); in nv35_gr_chan_new()
42 nvkm_wo32(chan->inst, 0x0028, 0x00000001 | (chan->chid << 24)); in nv35_gr_chan_new()
43 nvkm_wo32(chan->inst, 0x040c, 0x00000101); in nv35_gr_chan_new()
[all …]
/linux/drivers/dma/stm32/
H A Dstm32-dma.c232 struct stm32_dma_chan chan[STM32_DMA_MAX_CHANNELS]; member
235 static struct stm32_dma_device *stm32_dma_get_dev(struct stm32_dma_chan *chan) in stm32_dma_get_dev() argument
237 return container_of(chan->vchan.chan.device, struct stm32_dma_device, in stm32_dma_get_dev()
243 return container_of(c, struct stm32_dma_chan, vchan.chan); in to_stm32_dma_chan()
251 static struct device *chan2dev(struct stm32_dma_chan *chan) in chan2dev() argument
253 return &chan->vchan.chan.dev->device; in chan2dev()
266 static int stm32_dma_get_width(struct stm32_dma_chan *chan, in stm32_dma_get_width() argument
277 dev_err(chan2dev(chan), "Dma bus width not supported\n"); in stm32_dma_get_width()
364 static int stm32_dma_get_burst(struct stm32_dma_chan *chan, u32 maxburst) in stm32_dma_get_burst() argument
377 dev_err(chan2dev(chan), "Dma burst size not supported\n"); in stm32_dma_get_burst()
[all …]
/linux/include/sound/
H A Demu8000_reg.h24 #define EMU8000_CMD(reg, chan) ((reg)<<5 | (chan)) argument
30 #define EMU8000_CPF_READ(emu, chan) \ argument
31 snd_emu8000_peek_dw((emu), EMU8000_DATA0(emu), EMU8000_CMD(0, (chan)))
32 #define EMU8000_PTRX_READ(emu, chan) \ argument
33 snd_emu8000_peek_dw((emu), EMU8000_DATA0(emu), EMU8000_CMD(1, (chan)))
34 #define EMU8000_CVCF_READ(emu, chan) \ argument
35 snd_emu8000_peek_dw((emu), EMU8000_DATA0(emu), EMU8000_CMD(2, (chan)))
36 #define EMU8000_VTFT_READ(emu, chan) \ argument
37 snd_emu8000_peek_dw((emu), EMU8000_DATA0(emu), EMU8000_CMD(3, (chan)))
38 #define EMU8000_PSST_READ(emu, chan) \ argument
[all …]
/linux/drivers/dma/dw-edma/
H A Ddw-hdma-v0-core.c52 static u32 dw_hdma_v0_core_int_setup(struct dw_edma_chan *chan, u32 val) in dw_hdma_v0_core_int_setup() argument
66 if (chan->irq_mode == DW_EDMA_CH_IRQ_REMOTE) in dw_hdma_v0_core_int_setup()
121 static int dw_hdma_v0_core_ch_quiesce(struct dw_edma_chan *chan) in dw_hdma_v0_core_ch_quiesce() argument
123 dw_hdma_v0_core_ch_off(chan->dw, chan->dir, chan->id); in dw_hdma_v0_core_ch_quiesce()
138 static enum dma_status dw_hdma_v0_core_ch_status(struct dw_edma_chan *chan) in dw_hdma_v0_core_ch_status() argument
140 struct dw_edma *dw = chan->dw; in dw_hdma_v0_core_ch_status()
144 GET_CH_32(dw, chan->dir, chan->id, ch_stat)); in dw_hdma_v0_core_ch_status()
154 static void dw_hdma_v0_core_clear_done_int(struct dw_edma_chan *chan) in dw_hdma_v0_core_clear_done_int() argument
156 struct dw_edma *dw = chan->dw; in dw_hdma_v0_core_clear_done_int()
158 SET_CH_32(dw, chan->dir, chan->id, int_clear, HDMA_V0_STOP_INT_MASK); in dw_hdma_v0_core_clear_done_int()
[all …]
/linux/drivers/video/fbdev/nvidia/
H A Dnv_i2c.c30 struct nvidia_i2c_chan *chan = data; in nvidia_gpio_setscl() local
31 struct nvidia_par *par = chan->par; in nvidia_gpio_setscl()
34 val = NVReadCrtc(par, chan->ddc_base + 1) & 0xf0; in nvidia_gpio_setscl()
41 NVWriteCrtc(par, chan->ddc_base + 1, val | 0x01); in nvidia_gpio_setscl()
46 struct nvidia_i2c_chan *chan = data; in nvidia_gpio_setsda() local
47 struct nvidia_par *par = chan->par; in nvidia_gpio_setsda()
50 val = NVReadCrtc(par, chan->ddc_base + 1) & 0xf0; in nvidia_gpio_setsda()
57 NVWriteCrtc(par, chan->ddc_base + 1, val | 0x01); in nvidia_gpio_setsda()
62 struct nvidia_i2c_chan *chan = data; in nvidia_gpio_getscl() local
63 struct nvidia_par *par = chan->par; in nvidia_gpio_getscl()
[all …]
/linux/drivers/dma/sf-pdma/
H A Dsf-pdma.c46 return container_of(dchan, struct sf_pdma_chan, vchan.chan); in to_sf_pdma_chan()
54 static struct sf_pdma_desc *sf_pdma_alloc_desc(struct sf_pdma_chan *chan) in sf_pdma_alloc_desc() argument
62 desc->chan = chan; in sf_pdma_alloc_desc()
70 desc->xfer_type = desc->chan->pdma->transfer_type; in sf_pdma_fill_desc()
76 static void sf_pdma_disclaim_chan(struct sf_pdma_chan *chan) in sf_pdma_disclaim_chan() argument
78 struct pdma_regs *regs = &chan->regs; in sf_pdma_disclaim_chan()
87 struct sf_pdma_chan *chan = to_sf_pdma_chan(dchan); in sf_pdma_prep_dma_memcpy() local
91 if (chan && (!len || !dest || !src)) { in sf_pdma_prep_dma_memcpy()
92 dev_err(chan->pdma->dma_dev.dev, in sf_pdma_prep_dma_memcpy()
97 desc = sf_pdma_alloc_desc(chan); in sf_pdma_prep_dma_memcpy()
[all …]
/linux/drivers/dma/dw-axi-dmac/
H A Ddw-axi-dmac-platform.c78 axi_chan_iowrite32(struct axi_dma_chan *chan, u32 reg, u32 val) in axi_chan_iowrite32() argument
80 iowrite32(val, chan->chan_regs + reg); in axi_chan_iowrite32()
83 static inline u32 axi_chan_ioread32(struct axi_dma_chan *chan, u32 reg) in axi_chan_ioread32() argument
85 return ioread32(chan->chan_regs + reg); in axi_chan_ioread32()
89 axi_chan_iowrite64(struct axi_dma_chan *chan, u32 reg, u64 val) in axi_chan_iowrite64() argument
95 iowrite32(lower_32_bits(val), chan->chan_regs + reg); in axi_chan_iowrite64()
96 iowrite32(upper_32_bits(val), chan->chan_regs + reg + 4); in axi_chan_iowrite64()
99 static inline void axi_chan_config_write(struct axi_dma_chan *chan, in axi_chan_config_write() argument
106 if (chan->chip->dw->hdata->reg_map_8_channels && in axi_chan_config_write()
107 !chan->chip->dw->hdata->use_cfg2) { in axi_chan_config_write()
[all …]

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