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Searched refs:chan (Results 1 – 25 of 1440) sorted by relevance

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/linux/drivers/dma/
H A Dfsldma.c39 #define chan_dbg(chan, fmt, arg...) \ argument
40 dev_dbg(chan->dev, "%s: " fmt, chan->name, ##arg)
41 #define chan_err(chan, fmt, arg...) \ argument
42 dev_err(chan->dev, "%s: " fmt, chan->name, ##arg)
50 static void set_sr(struct fsldma_chan *chan, u32 val) in set_sr() argument
52 FSL_DMA_OUT(chan, &chan->regs->sr, val, 32); in set_sr()
55 static u32 get_sr(struct fsldma_chan *chan) in get_sr() argument
57 return FSL_DMA_IN(chan, &chan->regs->sr, 32); in get_sr()
60 static void set_mr(struct fsldma_chan *chan, u32 val) in set_mr() argument
62 FSL_DMA_OUT(chan, &chan->regs->mr, val, 32); in set_mr()
[all …]
/linux/drivers/gpu/drm/nouveau/
H A Dnouveau_chan.c44 nouveau_channel_kill(struct nouveau_channel *chan) in nouveau_channel_kill() argument
46 atomic_set(&chan->killed, 1); in nouveau_channel_kill()
47 if (chan->fence) in nouveau_channel_kill()
48 nouveau_fence_context_kill(chan->fence, -ENODEV); in nouveau_channel_kill()
54 struct nouveau_channel *chan = container_of(event, typeof(*chan), kill); in nouveau_channel_killed() local
55 struct nouveau_cli *cli = chan->cli; in nouveau_channel_killed()
57 NV_PRINTK(warn, cli, "channel %d killed!\n", chan->chid); in nouveau_channel_killed()
59 if (unlikely(!atomic_read(&chan->killed))) in nouveau_channel_killed()
60 nouveau_channel_kill(chan); in nouveau_channel_killed()
66 nouveau_channel_idle(struct nouveau_channel *chan) in nouveau_channel_idle() argument
[all …]
H A Dnouveau_dma.c41 READ_GET(struct nouveau_channel *chan, uint64_t *prev_get, int *timeout) in READ_GET() argument
45 val = nvif_rd32(chan->userd, chan->user_get); in READ_GET()
46 if (chan->user_get_hi) in READ_GET()
47 val |= (uint64_t)nvif_rd32(chan->userd, chan->user_get_hi) << 32; in READ_GET()
64 if (val < chan->push.addr || in READ_GET()
65 val > chan->push.addr + (chan->dma.max << 2)) in READ_GET()
68 return (val - chan in READ_GET()
72 nv50_dma_push(struct nouveau_channel * chan,u64 offset,u32 length,bool no_prefetch) nv50_dma_push() argument
99 nv50_dma_push_wait(struct nouveau_channel * chan,int count) nv50_dma_push_wait() argument
125 nv50_dma_wait(struct nouveau_channel * chan,int slots,int count) nv50_dma_wait() argument
168 nouveau_dma_wait(struct nouveau_channel * chan,int slots,int size) nouveau_dma_wait() argument
[all...]
/linux/arch/um/drivers/
H A Dchan_kern.c90 static int open_one_chan(struct chan *chan) in open_one_chan() argument
94 if (chan->opened) in open_one_chan()
97 if (chan->ops->open == NULL) in open_one_chan()
99 else fd = (*chan->ops->open)(chan->input, chan->output, chan->primary, in open_one_chan()
100 chan->data, &chan->dev); in open_one_chan()
108 chan->fd_in = fd; in open_one_chan()
109 chan->fd_out = fd; in open_one_chan()
122 if (chan->output && need_output_blocking()) { in open_one_chan()
123 err = os_dup_file(chan->fd_out); in open_one_chan()
127 chan->fd_out = err; in open_one_chan()
[all …]
/linux/net/bluetooth/
H A Dl2cap_core.c57 static int l2cap_build_conf_req(struct l2cap_chan *chan, void *data, size_t data_size);
58 static void l2cap_send_disconn_req(struct l2cap_chan *chan, int err);
60 static void l2cap_tx(struct l2cap_chan *chan, struct l2cap_ctrl *control,
186 int l2cap_add_psm(struct l2cap_chan *chan, bdaddr_t *src, __le16 psm) in l2cap_add_psm() argument
192 if (psm && __l2cap_global_chan_by_addr(psm, src, chan->src_type)) { in l2cap_add_psm()
198 chan->psm = psm; in l2cap_add_psm()
199 chan->sport = psm; in l2cap_add_psm()
204 if (chan->src_type == BDADDR_BREDR) { in l2cap_add_psm()
217 chan->src_type)) { in l2cap_add_psm()
218 chan->psm = cpu_to_le16(p); in l2cap_add_psm()
[all …]
H A Dl2cap_sock.c86 struct l2cap_chan *chan = l2cap_pi(sk)->chan; in l2cap_sock_bind() local
132 bacpy(&chan->src, &la.l2_bdaddr); in l2cap_sock_bind()
133 chan->src_type = la.l2_bdaddr_type; in l2cap_sock_bind()
136 err = l2cap_add_scid(chan, __le16_to_cpu(la.l2_cid)); in l2cap_sock_bind()
138 err = l2cap_add_psm(chan, &la.l2_bdaddr, la.l2_psm); in l2cap_sock_bind()
143 switch (chan->chan_type) { in l2cap_sock_bind()
146 chan->sec_level = BT_SECURITY_SDP; in l2cap_sock_bind()
151 chan->sec_level = BT_SECURITY_SDP; in l2cap_sock_bind()
154 chan->sec_level = BT_SECURITY_SDP; in l2cap_sock_bind()
162 set_bit(FLAG_HOLD_HCI_CONN, &chan->flags); in l2cap_sock_bind()
[all …]
/linux/drivers/gpu/drm/nouveau/nvkm/engine/fifo/
H A Dchan.c41 nvkm_chan_cctx_bind(struct nvkm_chan *chan, struct nvkm_engn *engn, struct nvkm_cctx *cctx) in nvkm_chan_cctx_bind() argument
43 struct nvkm_cgrp *cgrp = chan->cgrp; in nvkm_chan_cctx_bind()
50 CHAN_TRACE(chan, "%sbind cctx %d[%s]", cctx ? "" : "un", engn->id, engine->subdev.name); in nvkm_chan_cctx_bind()
58 nvkm_chan_block(chan); in nvkm_chan_cctx_bind()
59 nvkm_chan_preempt(chan, true); in nvkm_chan_cctx_bind()
62 engn->func->bind(engn, cctx, chan); in nvkm_chan_cctx_bind()
68 nvkm_chan_allow(chan); in nvkm_chan_cctx_bind()
72 nvkm_chan_cctx_put(struct nvkm_chan *chan, struct nvkm_cctx **pcctx) in nvkm_chan_cctx_put() argument
79 if (refcount_dec_and_mutex_lock(&cctx->refs, &chan->cgrp->mutex)) { in nvkm_chan_cctx_put()
80 CHAN_TRACE(chan, "dtor cctx %d[%s]", engn->id, engn->engine->subdev.name); in nvkm_chan_cctx_put()
[all …]
/linux/sound/soc/qcom/
H A Dlpass-lpaif-reg.h102 #define LPAIF_IRQ_PER(chan) (1 << (LPAIF_IRQ_BITSTRIDE * (chan))) argument
103 #define LPAIF_IRQ_XRUN(chan) (2 << (LPAIF_IRQ_BITSTRIDE * (chan))) argument
104 #define LPAIF_IRQ_ERR(chan) (4 << (LPAIF_IRQ_BITSTRIDE * (chan))) argument
106 #define LPAIF_IRQ_ALL(chan) (7 << (LPAIF_IRQ_BITSTRIDE * (chan))) argument
107 #define LPAIF_IRQ_HDMI_REQ_ON_PRELOAD(chan) (1 << (14 + chan)) argument
108 #define LPAIF_IRQ_HDMI_SDEEP_AUD_DIS(chan) (1 << (24 + chan)) argument
112 #define LPAIF_HDMI_RDMA_REG_ADDR(v, addr, chan) \ argument
113 (v->hdmi_rdma_reg_base + (addr) + v->hdmi_rdma_reg_stride * (chan))
117 #define LPAIF_HDMI_RDMACTL_REG(v, chan) LPAIF_HDMI_RDMA_REG_ADDR(v, 0x00, (chan)) argument
118 #define LPAIF_HDMI_RDMABASE_REG(v, chan) LPAIF_HDMI_RDMA_REG_ADDR(v, 0x04, (chan)) argument
[all …]
/linux/drivers/video/fbdev/savage/
H A Dsavagefb-i2c.c47 struct savagefb_i2c_chan *chan = data; in savage4_gpio_setscl() local
50 r = readl(chan->ioaddr + chan->reg); in savage4_gpio_setscl()
55 writel(r, chan->ioaddr + chan->reg); in savage4_gpio_setscl()
56 readl(chan->ioaddr + chan->reg); /* flush posted write */ in savage4_gpio_setscl()
61 struct savagefb_i2c_chan *chan = data; in savage4_gpio_setsda() local
64 r = readl(chan->ioaddr + chan->reg); in savage4_gpio_setsda()
69 writel(r, chan->ioaddr + chan->reg); in savage4_gpio_setsda()
70 readl(chan->ioaddr + chan->reg); /* flush posted write */ in savage4_gpio_setsda()
75 struct savagefb_i2c_chan *chan = data; in savage4_gpio_getscl() local
77 return (0 != (readl(chan->ioaddr + chan->reg) & SAVAGE4_I2C_SCL_IN)); in savage4_gpio_getscl()
[all …]
/linux/drivers/mailbox/
H A Dmailbox.c27 static int add_to_rbuf(struct mbox_chan *chan, void *mssg) in add_to_rbuf() argument
32 spin_lock_irqsave(&chan->lock, flags); in add_to_rbuf()
35 if (chan->msg_count == MBOX_TX_QUEUE_LEN) { in add_to_rbuf()
36 spin_unlock_irqrestore(&chan->lock, flags); in add_to_rbuf()
40 idx = chan->msg_free; in add_to_rbuf()
41 chan->msg_data[idx] = mssg; in add_to_rbuf()
42 chan->msg_count++; in add_to_rbuf()
45 chan->msg_free = 0; in add_to_rbuf()
47 chan->msg_free++; in add_to_rbuf()
49 spin_unlock_irqrestore(&chan->lock, flags); in add_to_rbuf()
[all …]
/linux/drivers/dma/xilinx/
H A Dxilinx_dma.c453 void (*start_transfer)(struct xilinx_dma_chan *chan);
454 int (*stop_transfer)(struct xilinx_dma_chan *chan);
509 struct xilinx_dma_chan *chan[XILINX_MCDMA_MAX_CHANS_PER_DEVICE]; member
526 #define to_xilinx_chan(chan) \ argument
527 container_of(chan, struct xilinx_dma_chan, common)
530 #define xilinx_dma_poll_timeout(chan, reg, val, cond, delay_us, timeout_us) \ argument
531 readl_poll_timeout_atomic(chan->xdev->regs + chan->ctrl_offset + reg, \
535 static inline u32 dma_read(struct xilinx_dma_chan *chan, u32 reg) in dma_read() argument
537 return ioread32(chan->xdev->regs + reg); in dma_read()
540 static inline void dma_write(struct xilinx_dma_chan *chan, u32 reg, u32 value) in dma_write() argument
[all …]
/linux/arch/sh/drivers/dma/
H A Ddma-sh.c39 static unsigned long dma_find_base(unsigned int chan) in dma_find_base() argument
44 if (chan >= SH_DMAC_NR_MD_CH) in dma_find_base()
51 static unsigned long dma_base_addr(unsigned int chan) in dma_base_addr() argument
53 unsigned long base = dma_find_base(chan); in dma_base_addr()
55 chan = (chan % SH_DMAC_NR_MD_CH) * SH_DMAC_CH_SZ; in dma_base_addr()
58 if (chan >= DMAOR) in dma_base_addr()
61 return base + chan; in dma_base_addr()
65 static inline unsigned int get_dmte_irq(unsigned int chan) in get_dmte_irq() argument
67 return chan >= 6 ? DMTE6_IRQ : DMTE0_IRQ; in get_dmte_irq()
87 static inline unsigned int get_dmte_irq(unsigned int chan) in get_dmte_irq() argument
[all …]
/linux/drivers/video/fbdev/i810/
H A Di810-i2c.c44 struct i810fb_i2c_chan *chan = data; in i810i2c_setscl() local
45 struct i810fb_par *par = chan->par; in i810i2c_setscl()
49 i810_writel(mmio, chan->ddc_base, SCL_DIR_MASK | SCL_VAL_MASK); in i810i2c_setscl()
51 i810_writel(mmio, chan->ddc_base, SCL_DIR | SCL_DIR_MASK | SCL_VAL_MASK); in i810i2c_setscl()
52 i810_readl(mmio, chan->ddc_base); /* flush posted write */ in i810i2c_setscl()
57 struct i810fb_i2c_chan *chan = data; in i810i2c_setsda() local
58 struct i810fb_par *par = chan->par; in i810i2c_setsda()
62 i810_writel(mmio, chan->ddc_base, SDA_DIR_MASK | SDA_VAL_MASK); in i810i2c_setsda()
64 i810_writel(mmio, chan->ddc_base, SDA_DIR | SDA_DIR_MASK | SDA_VAL_MASK); in i810i2c_setsda()
65 i810_readl(mmio, chan->ddc_base); /* flush posted write */ in i810i2c_setsda()
[all …]
/linux/drivers/dma/stm32/
H A Dstm32-dma.c232 struct stm32_dma_chan chan[STM32_DMA_MAX_CHANNELS]; member
235 static struct stm32_dma_device *stm32_dma_get_dev(struct stm32_dma_chan *chan) in stm32_dma_get_dev() argument
237 return container_of(chan->vchan.chan.device, struct stm32_dma_device, in stm32_dma_get_dev()
243 return container_of(c, struct stm32_dma_chan, vchan.chan); in to_stm32_dma_chan()
251 static struct device *chan2dev(struct stm32_dma_chan *chan) in chan2dev() argument
253 return &chan->vchan.chan.dev->device; in chan2dev()
266 static int stm32_dma_get_width(struct stm32_dma_chan *chan, in stm32_dma_get_width() argument
277 dev_err(chan2dev(chan), "Dma bus width not supported\n"); in stm32_dma_get_width()
364 static int stm32_dma_get_burst(struct stm32_dma_chan *chan, u32 maxburst) in stm32_dma_get_burst() argument
377 dev_err(chan2dev(chan), "Dma burst size not supported\n"); in stm32_dma_get_burst()
[all …]
/linux/arch/mips/include/asm/mach-au1x00/
H A Dau1000_dma.h155 struct dma_chan *chan = get_dma_chan(dmanr); in enable_dma_buffer0() local
157 if (!chan) in enable_dma_buffer0()
159 __raw_writel(DMA_BE0, chan->io + DMA_MODE_SET); in enable_dma_buffer0()
164 struct dma_chan *chan = get_dma_chan(dmanr); in enable_dma_buffer1() local
166 if (!chan) in enable_dma_buffer1()
168 __raw_writel(DMA_BE1, chan->io + DMA_MODE_SET); in enable_dma_buffer1()
172 struct dma_chan *chan = get_dma_chan(dmanr); in enable_dma_buffers() local
174 if (!chan) in enable_dma_buffers()
176 __raw_writel(DMA_BE0 | DMA_BE1, chan->io + DMA_MODE_SET); in enable_dma_buffers()
181 struct dma_chan *chan = get_dma_chan(dmanr); in start_dma() local
[all …]
/linux/include/sound/
H A Demu8000_reg.h24 #define EMU8000_CMD(reg, chan) ((reg)<<5 | (chan)) argument
30 #define EMU8000_CPF_READ(emu, chan) \ argument
31 snd_emu8000_peek_dw((emu), EMU8000_DATA0(emu), EMU8000_CMD(0, (chan)))
32 #define EMU8000_PTRX_READ(emu, chan) \ argument
33 snd_emu8000_peek_dw((emu), EMU8000_DATA0(emu), EMU8000_CMD(1, (chan)))
34 #define EMU8000_CVCF_READ(emu, chan) \ argument
35 snd_emu8000_peek_dw((emu), EMU8000_DATA0(emu), EMU8000_CMD(2, (chan)))
36 #define EMU8000_VTFT_READ(emu, chan) \ argument
37 snd_emu8000_peek_dw((emu), EMU8000_DATA0(emu), EMU8000_CMD(3, (chan)))
38 #define EMU8000_PSST_READ(emu, chan) \ argument
[all …]
/linux/drivers/gpu/drm/gma500/
H A Doaktrail_lvds_i2c.c63 #define LPC_READ_REG(chan, r) inl((chan)->reg + (r)) argument
64 #define LPC_WRITE_REG(chan, r, val) outl((val), (chan)->reg + (r)) argument
68 struct gma_i2c_chan *chan = data; in get_clock() local
71 val = LPC_READ_REG(chan, RGIO); in get_clock()
73 LPC_WRITE_REG(chan, RGIO, val); in get_clock()
74 LPC_READ_REG(chan, RGLVL); in get_clock()
75 val = (LPC_READ_REG(chan, RGLVL) & GPIO_CLOCK) ? 1 : 0; in get_clock()
82 struct gma_i2c_chan *chan = data; in get_data() local
85 val = LPC_READ_REG(chan, RGIO); in get_data()
87 LPC_WRITE_REG(chan, RGIO, val); in get_data()
[all …]
H A Dintel_i2c.c25 struct gma_i2c_chan *chan = data; in get_clock() local
26 struct drm_device *dev = chan->drm_dev; in get_clock()
29 val = REG_READ(chan->reg); in get_clock()
35 struct gma_i2c_chan *chan = data; in get_data() local
36 struct drm_device *dev = chan->drm_dev; in get_data()
39 val = REG_READ(chan->reg); in get_data()
45 struct gma_i2c_chan *chan = data; in set_clock() local
46 struct drm_device *dev = chan->drm_dev; in set_clock()
51 REG_READ(chan->reg) & (GPIO_DATA_PULLUP_DISABLE | in set_clock()
59 REG_WRITE(chan->reg, reserved | clock_bits); in set_clock()
[all …]
/linux/drivers/gpu/drm/nouveau/nvkm/engine/gr/
H A Dnv25.c25 struct nv20_gr_chan *chan; in nv25_gr_chan_new() local
28 if (!(chan = kzalloc(sizeof(*chan), GFP_KERNEL))) in nv25_gr_chan_new()
30 nvkm_object_ctor(&nv25_gr_chan, oclass, &chan->object); in nv25_gr_chan_new()
31 chan->gr = gr; in nv25_gr_chan_new()
32 chan->chid = fifoch->id; in nv25_gr_chan_new()
33 *pobject = &chan->object; in nv25_gr_chan_new()
37 &chan->inst); in nv25_gr_chan_new()
41 nvkm_kmap(chan->inst); in nv25_gr_chan_new()
42 nvkm_wo32(chan->inst, 0x0028, 0x00000001 | (chan->chid << 24)); in nv25_gr_chan_new()
43 nvkm_wo32(chan->inst, 0x035c, 0xffff0000); in nv25_gr_chan_new()
[all …]
H A Dnv35.c25 struct nv20_gr_chan *chan; in nv35_gr_chan_new() local
28 if (!(chan = kzalloc(sizeof(*chan), GFP_KERNEL))) in nv35_gr_chan_new()
30 nvkm_object_ctor(&nv35_gr_chan, oclass, &chan->object); in nv35_gr_chan_new()
31 chan->gr = gr; in nv35_gr_chan_new()
32 chan->chid = fifoch->id; in nv35_gr_chan_new()
33 *pobject = &chan->object; in nv35_gr_chan_new()
37 &chan->inst); in nv35_gr_chan_new()
41 nvkm_kmap(chan->inst); in nv35_gr_chan_new()
42 nvkm_wo32(chan->inst, 0x0028, 0x00000001 | (chan->chid << 24)); in nv35_gr_chan_new()
43 nvkm_wo32(chan->inst, 0x040c, 0x00000101); in nv35_gr_chan_new()
[all …]
H A Dnv34.c25 struct nv20_gr_chan *chan; in nv34_gr_chan_new() local
28 if (!(chan = kzalloc(sizeof(*chan), GFP_KERNEL))) in nv34_gr_chan_new()
30 nvkm_object_ctor(&nv34_gr_chan, oclass, &chan->object); in nv34_gr_chan_new()
31 chan->gr = gr; in nv34_gr_chan_new()
32 chan->chid = fifoch->id; in nv34_gr_chan_new()
33 *pobject = &chan->object; in nv34_gr_chan_new()
37 &chan->inst); in nv34_gr_chan_new()
41 nvkm_kmap(chan->inst); in nv34_gr_chan_new()
42 nvkm_wo32(chan->inst, 0x0028, 0x00000001 | (chan->chid << 24)); in nv34_gr_chan_new()
43 nvkm_wo32(chan->inst, 0x040c, 0x01000101); in nv34_gr_chan_new()
[all …]
/linux/drivers/staging/media/tegra-video/
H A Dtegra20.c151 static void tegra20_vi_write(struct tegra_vi_channel *chan, unsigned int addr, u32 val) in tegra20_vi_write() argument
153 writel(val, chan->vi->iomem + addr); in tegra20_vi_write()
160 static void tegra20_vi_get_input_formats(struct tegra_vi_channel *chan, in tegra20_vi_get_input_formats() argument
164 unsigned int input_mbus_code = chan->fmtinfo->code; in tegra20_vi_get_input_formats()
189 static void tegra20_vi_get_output_formats(struct tegra_vi_channel *chan, in tegra20_vi_get_output_formats() argument
193 u32 output_fourcc = chan->format.pixelformat; in tegra20_vi_get_output_formats()
251 static int tegra20_channel_host1x_syncpt_init(struct tegra_vi_channel *chan) in tegra20_channel_host1x_syncpt_init() argument
253 struct tegra_vi *vi = chan->vi; in tegra20_channel_host1x_syncpt_init()
260 chan->mw_ack_sp[0] = out_sp; in tegra20_channel_host1x_syncpt_init()
265 static void tegra20_channel_host1x_syncpt_free(struct tegra_vi_channel *chan) in tegra20_channel_host1x_syncpt_free() argument
[all …]
H A Dvi.c112 struct tegra_vi_channel *chan = vb2_get_drv_priv(vq); in tegra_channel_queue_setup() local
115 return sizes[0] < chan->format.sizeimage ? -EINVAL : 0; in tegra_channel_queue_setup()
118 sizes[0] = chan->format.sizeimage; in tegra_channel_queue_setup()
119 alloc_devs[0] = chan->vi->dev; in tegra_channel_queue_setup()
121 if (chan->vi->ops->channel_queue_setup) in tegra_channel_queue_setup()
122 chan->vi->ops->channel_queue_setup(chan); in tegra_channel_queue_setup()
129 struct tegra_vi_channel *chan = vb2_get_drv_priv(vb->vb2_queue); in tegra_channel_buffer_prepare() local
132 unsigned long size = chan->format.sizeimage; in tegra_channel_buffer_prepare()
135 v4l2_err(chan->video.v4l2_dev, in tegra_channel_buffer_prepare()
142 buf->chan = chan; in tegra_channel_buffer_prepare()
[all …]
/linux/drivers/dma/sf-pdma/
H A Dsf-pdma.c47 return container_of(dchan, struct sf_pdma_chan, vchan.chan); in to_sf_pdma_chan()
55 static struct sf_pdma_desc *sf_pdma_alloc_desc(struct sf_pdma_chan *chan) in sf_pdma_alloc_desc() argument
63 desc->chan = chan; in sf_pdma_alloc_desc()
71 desc->xfer_type = desc->chan->pdma->transfer_type; in sf_pdma_fill_desc()
77 static void sf_pdma_disclaim_chan(struct sf_pdma_chan *chan) in sf_pdma_disclaim_chan() argument
79 struct pdma_regs *regs = &chan->regs; in sf_pdma_disclaim_chan()
88 struct sf_pdma_chan *chan = to_sf_pdma_chan(dchan); in sf_pdma_prep_dma_memcpy() local
92 if (chan && (!len || !dest || !src)) { in sf_pdma_prep_dma_memcpy()
93 dev_err(chan->pdma->dma_dev.dev, in sf_pdma_prep_dma_memcpy()
98 desc = sf_pdma_alloc_desc(chan); in sf_pdma_prep_dma_memcpy()
[all …]
/linux/drivers/video/fbdev/nvidia/
H A Dnv_i2c.c30 struct nvidia_i2c_chan *chan = data; in nvidia_gpio_setscl() local
31 struct nvidia_par *par = chan->par; in nvidia_gpio_setscl()
34 val = NVReadCrtc(par, chan->ddc_base + 1) & 0xf0; in nvidia_gpio_setscl()
41 NVWriteCrtc(par, chan->ddc_base + 1, val | 0x01); in nvidia_gpio_setscl()
46 struct nvidia_i2c_chan *chan = data; in nvidia_gpio_setsda() local
47 struct nvidia_par *par = chan->par; in nvidia_gpio_setsda()
50 val = NVReadCrtc(par, chan->ddc_base + 1) & 0xf0; in nvidia_gpio_setsda()
57 NVWriteCrtc(par, chan->ddc_base + 1, val | 0x01); in nvidia_gpio_setsda()
62 struct nvidia_i2c_chan *chan = data; in nvidia_gpio_getscl() local
63 struct nvidia_par *par = chan->par; in nvidia_gpio_getscl()
[all …]

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