| /linux/drivers/gpu/drm/amd/amdgpu/ |
| H A D | umc_v8_7.c | 45 uint32_t ch_inst) in get_umc_v8_7_reg_offset() argument
47 return adev->umc.channel_offs*ch_inst + UMC_8_INST_DIST*umc_inst; in get_umc_v8_7_reg_offset()
51 uint32_t umc_inst, uint32_t ch_inst, in umc_v8_7_ecc_info_query_correctable_error_count() argument
58 eccinfo_table_idx = umc_inst * adev->umc.channel_inst_num + ch_inst; in umc_v8_7_ecc_info_query_correctable_error_count()
70 uint32_t umc_inst, uint32_t ch_inst, in umc_v8_7_ecc_info_querry_uncorrectable_error_count() argument
77 eccinfo_table_idx = umc_inst * adev->umc.channel_inst_num + ch_inst; in umc_v8_7_ecc_info_querry_uncorrectable_error_count()
96 uint32_t ch_inst = 0; in umc_v8_7_ecc_info_query_ras_error_count() local
101 LOOP_UMC_INST_AND_CH(umc_inst, ch_inst) { in umc_v8_7_ecc_info_query_ras_error_count()
103 umc_inst, ch_inst, in umc_v8_7_ecc_info_query_ras_error_count()
106 umc_inst, ch_inst, in umc_v8_7_ecc_info_query_ras_error_count()
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| H A D | umc_v6_7.c | 48 uint32_t ch_inst) in get_umc_v6_7_reg_offset() argument
50 uint32_t index = umc_inst * adev->umc.channel_inst_num + ch_inst; in get_umc_v6_7_reg_offset()
55 ch_inst = index % 4; in get_umc_v6_7_reg_offset()
57 return adev->umc.channel_offs * ch_inst + UMC_V6_7_INST_DIST * umc_inst; in get_umc_v6_7_reg_offset()
95 uint32_t umc_inst, uint32_t ch_inst, in umc_v6_7_ecc_info_query_correctable_error_count() argument
104 umc_inst, ch_inst); in umc_v6_7_ecc_info_query_correctable_error_count()
106 eccinfo_table_idx = umc_inst * adev->umc.channel_inst_num + ch_inst; in umc_v6_7_ecc_info_query_correctable_error_count()
119 adev->umc.channel_idx_tbl[umc_inst * adev->umc.channel_inst_num + ch_inst]; in umc_v6_7_ecc_info_query_correctable_error_count()
137 uint32_t umc_inst, uint32_t ch_inst, in umc_v6_7_ecc_info_querry_uncorrectable_error_count() argument
146 umc_inst, ch_inst); in umc_v6_7_ecc_info_querry_uncorrectable_error_count()
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| H A D | umc_v8_10.c | 73 uint32_t ch_inst) in get_umc_v8_10_reg_offset() argument
75 return adev->umc.channel_offs * ch_inst + UMC_8_INST_DIST * umc_inst + in get_umc_v8_10_reg_offset()
81 uint32_t ch_inst, void *data) in umc_v8_10_clear_error_count_per_channel() argument
85 get_umc_v8_10_reg_offset(adev, node_inst, umc_inst, ch_inst); in umc_v8_10_clear_error_count_per_channel()
145 uint32_t ch_inst, void *data) in umc_v8_10_query_ecc_error_count() argument
149 get_umc_v8_10_reg_offset(adev, node_inst, umc_inst, ch_inst); in umc_v8_10_query_ecc_error_count()
207 uint32_t ch_inst, uint32_t umc_inst, in umc_v8_10_convert_error_address() argument
219 ch_inst]; in umc_v8_10_convert_error_address()
246 uint32_t ch_inst, void *data) in umc_v8_10_query_error_address() argument
253 get_umc_v8_10_reg_offset(adev, node_inst, umc_inst, ch_inst); in umc_v8_10_query_error_address()
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| H A D | umc_v6_1.c | 89 uint32_t ch_inst) in get_umc_6_reg_offset() argument
91 return adev->umc.channel_offs*ch_inst + UMC_6_INST_DIST*umc_inst; in get_umc_6_reg_offset()
148 uint32_t ch_inst = 0; in umc_v6_1_clear_error_count() local
156 LOOP_UMC_INST_AND_CH(umc_inst, ch_inst) { in umc_v6_1_clear_error_count()
159 ch_inst); in umc_v6_1_clear_error_count()
260 uint32_t ch_inst = 0; in umc_v6_1_query_ras_error_count() local
272 LOOP_UMC_INST_AND_CH(umc_inst, ch_inst) { in umc_v6_1_query_ras_error_count()
275 ch_inst); in umc_v6_1_query_ras_error_count()
298 uint32_t ch_inst, in umc_v6_1_query_error_address() argument
303 …uint32_t channel_index = adev->umc.channel_idx_tbl[umc_inst * adev->umc.channel_inst_num + ch_inst… in umc_v6_1_query_error_address()
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| H A D | umc_v8_14.c | 32 uint32_t ch_inst) in get_umc_v8_14_reg_offset() argument
34 return adev->umc.channel_offs * ch_inst + UMC_V8_14_INST_DIST * umc_inst; in get_umc_v8_14_reg_offset()
39 uint32_t ch_inst, void *data) in umc_v8_14_clear_error_count_per_channel() argument
43 get_umc_v8_14_reg_offset(adev, umc_inst, ch_inst); in umc_v8_14_clear_error_count_per_channel()
94 uint32_t ch_inst, void *data) in umc_v8_14_query_error_count_per_channel() argument
98 get_umc_v8_14_reg_offset(adev, umc_inst, ch_inst); in umc_v8_14_query_error_count_per_channel()
121 uint32_t ch_inst, void *data) in umc_v8_14_err_cnt_init_per_channel() argument
126 get_umc_v8_14_reg_offset(adev, umc_inst, ch_inst); in umc_v8_14_err_cnt_init_per_channel()
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| H A D | umc_v6_7.h | 76 uint32_t ch_inst, uint32_t umc_inst);
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| H A D | amdgpu_ras.c | 3018 addr_in.ma.ch_inst = bps->mem_channel; in amdgpu_ras_mca2pa_by_idx()
3059 addr_in.ma.ch_inst = bps->mem_channel; in amdgpu_ras_mca2pa()
4924 uint32_t umc_inst = 0, ch_inst = 0; in amdgpu_bad_page_notifier() local
4958 ch_inst = GET_CHAN_INDEX(m->ipid); in amdgpu_bad_page_notifier()
4961 umc_inst, ch_inst); in amdgpu_bad_page_notifier()
4963 if (!amdgpu_umc_page_retirement_mca(adev, m->addr, ch_inst, umc_inst)) in amdgpu_bad_page_notifier()
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