Searched refs:cfg_val (Results 1 – 6 of 6) sorted by relevance
| /linux/drivers/gpu/drm/mediatek/ |
| H A D | mtk_disp_aal.c | 101 u32 cfg_val; in mtk_aal_gamma_set() local 126 cfg_val = readl(aal->regs + DISP_AAL_CFG); in mtk_aal_gamma_set() 129 cfg_val |= FIELD_PREP(AAL_GAMMA_LUT_EN, 1); in mtk_aal_gamma_set() 132 cfg_val &= ~AAL_RELAY_MODE; in mtk_aal_gamma_set() 134 writel(cfg_val, aal->regs + DISP_AAL_CFG); in mtk_aal_gamma_set()
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| /linux/sound/x86/ |
| H A D | intel_hdmi_audio.c | 350 union aud_cfg cfg_val = {.regval = 0}; in had_init_audio_ctrl() local 362 cfg_val.regx.num_ch = channels - 2; in had_init_audio_ctrl() 364 cfg_val.regx.layout = LAYOUT0; in had_init_audio_ctrl() 366 cfg_val.regx.layout = LAYOUT1; in had_init_audio_ctrl() 369 cfg_val.regx.packet_mode = 1; in had_init_audio_ctrl() 372 cfg_val.regx.left_align = 1; in had_init_audio_ctrl() 374 cfg_val.regx.val_bit = 1; in had_init_audio_ctrl() 378 cfg_val.regx.dp_modei = 1; in had_init_audio_ctrl() 379 cfg_val.regx.set = 1; in had_init_audio_ctrl() 382 had_write_register(intelhaddata, AUD_CONFIG, cfg_val.regval); in had_init_audio_ctrl() [all …]
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| /linux/drivers/pinctrl/bcm/ |
| H A D | pinctrl-bcm281xx.c | 2008 u32 cfg_val, cfg_mask; in bcm281xx_pinctrl_pin_config_set() local 2011 cfg_val = 0; in bcm281xx_pinctrl_pin_config_set() 2019 num_configs, &cfg_val, &cfg_mask); in bcm281xx_pinctrl_pin_config_set() 2025 num_configs, &cfg_val, &cfg_mask); in bcm281xx_pinctrl_pin_config_set() 2028 num_configs, &cfg_val, &cfg_mask); in bcm281xx_pinctrl_pin_config_set() 2033 num_configs, &cfg_val, &cfg_mask); in bcm281xx_pinctrl_pin_config_set() 2048 __func__, pdata->info->pins[pin].name, pin, cfg_val, cfg_mask); in bcm281xx_pinctrl_pin_config_set() 2058 rc = regmap_update_bits(pdata->regmap, offset, cfg_mask, cfg_val); in bcm281xx_pinctrl_pin_config_set()
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| /linux/drivers/clk/xilinx/ |
| H A D | xlnx_vcu.c | 292 u32 cfg_val; in xvcu_pll_set_div() local 303 cfg_val = FIELD_PREP(VCU_PLL_CFG_RES, cfg->res) | in xvcu_pll_set_div() 308 xvcu_write(base, VCU_PLL_CFG, cfg_val); in xvcu_pll_set_div()
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| /linux/arch/loongarch/kernel/ |
| H A D | ptrace.c | 234 u32 cfg_val; in cfg_get() local 238 cfg_val = read_cpucfg(i++); in cfg_get() 239 r = membuf_write(&to, &cfg_val, sizeof(u32)); in cfg_get()
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| /linux/drivers/net/ethernet/broadcom/ |
| H A D | tg3.c | 9289 u32 cfg_val; in tg3_chip_reset() local 9295 pci_read_config_dword(tp->pdev, 0xc4, &cfg_val); in tg3_chip_reset() 9297 cfg_val | (1 << 15)); in tg3_chip_reset()
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