Searched refs:cfg_space (Results 1 – 5 of 5) sorted by relevance
43 static void *cfg_space; variable57 return *(u32 *)(cfg_space + (addr&~3)); in READCFG32()62 *(u32 *)(cfg_space + (addr & ~3)) = data; in WRITECFG32()205 cfg_space = ioremap(A_BCM1480_PHYS_PCI_CFG_MATCH_BITS, 16*1024*1024); in bcm1480_pcibios_init()219 iounmap(cfg_space); in bcm1480_pcibios_init()
43 static void *cfg_space; variable67 return *(u32 *) (cfg_space + (addr & ~3)); in READCFG32()72 *(u32 *) (cfg_space + (addr & ~3)) = data; in WRITECFG32()213 cfg_space = in sb1250_pcibios_init()230 iounmap(cfg_space); in sb1250_pcibios_init()
5 gvt/cfg_space.o \
730 start_lo = (*(u32 *)(vgpu->cfg_space.virtual_cfg_space + bar)) & in intel_vgpu_get_bar_addr()732 mem_type = (*(u32 *)(vgpu->cfg_space.virtual_cfg_space + bar)) & in intel_vgpu_get_bar_addr()737 start_hi = (*(u32 *)(vgpu->cfg_space.virtual_cfg_space in intel_vgpu_get_bar_addr()1164 info->size = vgpu->cfg_space.bar[info->index].size; in intel_vgpu_ioctl_get_region_info()
638 struct resource cfg_space; member1234 mbase = ioremap(port->cfg_space.start + 0x10000000, 0x1000); in ppc460sx_pciex_check_link()1271 void __iomem *mbase = ioremap(port->cfg_space.start + 0x10000000, in ppc_476fpe_pciex_check_link()1357 RES_TO_U32_HIGH(port->cfg_space.start)); in ppc4xx_pciex_port_init_mapping()1359 RES_TO_U32_LOW(port->cfg_space.start)); in ppc4xx_pciex_port_init_mapping()1849 cfg_data = ioremap(port->cfg_space.start + in ppc4xx_pciex_port_setup_hose()1863 mbase = ioremap(port->cfg_space.start + 0x10000000, 0x1000); in ppc4xx_pciex_port_setup_hose()2028 if (of_address_to_resource(np, 0, &port->cfg_space)) { in ppc4xx_probe_pciex_bridge()