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Searched refs:cfgPSWUSCFG0_0_LANE_15_MARGINING_LANE_CNTL (Results 1 – 2 of 2) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/nbio/
H A Dnbio_2_3_offset.h913 #define cfgPSWUSCFG0_0_LANE_15_MARGINING_LANE_CNTL … macro
H A Dnbio_4_3_0_offset.h2741 #define cfgPSWUSCFG0_0_LANE_15_MARGINING_LANE_CNTL … macro