Searched refs:cdiv (Results 1 – 3 of 3) sorted by relevance
| /linux/drivers/clk/qcom/ |
| H A D | gcc-ipq4019.c | 31 struct clk_fepll, cdiv)
73 struct clk_regmap_div cdiv; member
91 u32 fdbkdiv, refclkdiv, cdiv; in clk_fepll_vco_calc_rate() local
94 regmap_read(pll_div->cdiv.clkr.regmap, pll_vco->reg, &cdiv); in clk_fepll_vco_calc_rate()
95 refclkdiv = (cdiv >> pll_vco->refclkdiv_shift) & in clk_fepll_vco_calc_rate()
97 fdbkdiv = (cdiv >> pll_vco->fdbkdiv_shift) & in clk_fepll_vco_calc_rate()
161 mask = (BIT(pll->cdiv.width) - 1) << pll->cdiv.shift; in clk_cpu_div_set_rate()
162 regmap_update_bits(pll->cdiv.clkr.regmap, in clk_cpu_div_set_rate()
163 pll->cdiv.reg, mask, in clk_cpu_div_set_rate()
164 f->pre_div << pll->cdiv.shift); in clk_cpu_div_set_rate()
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| /linux/drivers/gpu/drm/mcde/ |
| H A D | mcde_clk_div.c | 19 struct mcde_clk_div *cdiv = container_of(hw, struct mcde_clk_div, hw); in mcde_clk_div_enable() local
20 struct mcde *mcde = cdiv->mcde; in mcde_clk_div_enable()
24 val = readl(mcde->regs + cdiv->cr); in mcde_clk_div_enable()
36 val |= cdiv->cr_div; in mcde_clk_div_enable()
38 writel(val, mcde->regs + cdiv->cr); in mcde_clk_div_enable()
85 struct mcde_clk_div *cdiv = container_of(hw, struct mcde_clk_div, hw); in mcde_clk_div_recalc_rate() local
86 struct mcde *mcde = cdiv->mcde; in mcde_clk_div_recalc_rate()
98 cr = readl(mcde->regs + cdiv->cr); in mcde_clk_div_recalc_rate()
112 struct mcde_clk_div *cdiv = container_of(hw, struct mcde_clk_div, hw); in mcde_clk_div_set_rate() local
127 cdiv->cr_div = cr; in mcde_clk_div_set_rate()
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| /linux/drivers/spi/ |
| H A D | spi-ingenic.c | 105 u32 cdiv, speed_hz = xfer->speed_hz ?: spi->max_speed_hz, in spi_ingenic_prepare_transfer() local
108 cdiv = clk_hz / (speed_hz * 2); in spi_ingenic_prepare_transfer()
109 cdiv = clamp(cdiv, 1u, 0x100u) - 1; in spi_ingenic_prepare_transfer()
111 regmap_write(priv->map, REG_SSIGR, cdiv); in spi_ingenic_prepare_transfer()
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