Searched refs:cdclk_state (Results 1 – 8 of 8) sorted by relevance
2829 struct intel_cdclk_state *cdclk_state = in intel_compute_min_cdclk() local2844 if (cdclk_state->min_cdclk[crtc->pipe] == min_cdclk) in intel_compute_min_cdclk()2847 cdclk_state->min_cdclk[crtc->pipe] = min_cdclk; in intel_compute_min_cdclk()2849 ret = intel_atomic_lock_global_state(&cdclk_state->base); in intel_compute_min_cdclk()2858 if (cdclk_state->bw_min_cdclk != min_cdclk) { in intel_compute_min_cdclk()2861 cdclk_state->bw_min_cdclk = min_cdclk; in intel_compute_min_cdclk()2863 ret = intel_atomic_lock_global_state(&cdclk_state->base); in intel_compute_min_cdclk()2869 min_cdclk = max(cdclk_state->force_min_cdclk, in intel_compute_min_cdclk()2870 cdclk_state->bw_min_cdclk); in intel_compute_min_cdclk()2872 min_cdclk = max(min_cdclk, cdclk_state->min_cdclk[pipe]); in intel_compute_min_cdclk()[all …]
263 const struct intel_cdclk_state *cdclk_state; in hsw_ips_compute_config() local265 cdclk_state = intel_atomic_get_cdclk_state(state); in hsw_ips_compute_config()266 if (IS_ERR(cdclk_state)) in hsw_ips_compute_config()267 return PTR_ERR(cdclk_state); in hsw_ips_compute_config()270 if (crtc_state->pixel_rate > cdclk_state->logical.cdclk * 95 / 100) in hsw_ips_compute_config()
160 struct intel_cdclk_state *cdclk_state = in intel_crtc_disable_noatomic_complete() local181 cdclk_state->min_cdclk[pipe] = 0; in intel_crtc_disable_noatomic_complete()182 cdclk_state->min_voltage_level[pipe] = 0; in intel_crtc_disable_noatomic_complete()183 cdclk_state->active_pipes &= ~BIT(pipe); in intel_crtc_disable_noatomic_complete()706 struct intel_cdclk_state *cdclk_state = in intel_modeset_readout_hw_state() local743 cdclk_state->active_pipes = active_pipes; in intel_modeset_readout_hw_state()901 cdclk_state->min_cdclk[crtc->pipe] = min_cdclk; in intel_modeset_readout_hw_state()902 cdclk_state->min_voltage_level[crtc->pipe] = in intel_modeset_readout_hw_state()
86 struct intel_cdclk_state *cdclk_state; in intel_display_driver_init_hw() local91 cdclk_state = to_intel_cdclk_state(display->cdclk.obj.state); in intel_display_driver_init_hw()95 cdclk_state->logical = cdclk_state->actual = display->cdclk.hw; in intel_display_driver_init_hw()
260 const struct intel_cdclk_state *cdclk_state; in intel_plane_calc_min_cdclk() local285 cdclk_state = intel_atomic_get_cdclk_state(state); in intel_plane_calc_min_cdclk()286 if (IS_ERR(cdclk_state)) in intel_plane_calc_min_cdclk()287 return PTR_ERR(cdclk_state); in intel_plane_calc_min_cdclk()298 cdclk_state->min_cdclk[crtc->pipe]) in intel_plane_calc_min_cdclk()306 cdclk_state->min_cdclk[crtc->pipe]); in intel_plane_calc_min_cdclk()
1270 const struct intel_cdclk_state *cdclk_state; in intel_bw_calc_min_cdclk() local1315 cdclk_state = intel_atomic_get_cdclk_state(state); in intel_bw_calc_min_cdclk()1316 if (IS_ERR(cdclk_state)) in intel_bw_calc_min_cdclk()1317 return PTR_ERR(cdclk_state); in intel_bw_calc_min_cdclk()1327 if (new_min_cdclk <= cdclk_state->bw_min_cdclk) in intel_bw_calc_min_cdclk()1332 new_min_cdclk, cdclk_state->bw_min_cdclk); in intel_bw_calc_min_cdclk()
929 struct intel_cdclk_state *cdclk_state; in glk_force_audio_cdclk_commit() local937 cdclk_state = intel_atomic_get_cdclk_state(state); in glk_force_audio_cdclk_commit()938 if (IS_ERR(cdclk_state)) in glk_force_audio_cdclk_commit()939 return PTR_ERR(cdclk_state); in glk_force_audio_cdclk_commit()941 cdclk_state->force_min_cdclk = enable ? 2 * 96000 : 0; in glk_force_audio_cdclk_commit()
1414 const struct intel_cdclk_state *cdclk_state; in intel_fbc_check_plane() local1416 cdclk_state = intel_atomic_get_cdclk_state(state); in intel_fbc_check_plane()1417 if (IS_ERR(cdclk_state)) in intel_fbc_check_plane()1418 return PTR_ERR(cdclk_state); in intel_fbc_check_plane()1420 if (crtc_state->pixel_rate >= cdclk_state->logical.cdclk * 95 / 100) { in intel_fbc_check_plane()