Searched refs:cdclk_state (Results 1 – 2 of 2) sorted by relevance
2674 const struct intel_cdclk_state *cdclk_state) in dg2_power_well_count() argument2676 return display->platform.dg2 ? hweight8(cdclk_state->active_pipes) : 0; in dg2_power_well_count()2937 struct intel_cdclk_state *cdclk_state; in intel_cdclk_update_crtc_min_cdclk() local2947 cdclk_state = intel_atomic_get_cdclk_state(state); in intel_cdclk_update_crtc_min_cdclk()2948 if (IS_ERR(cdclk_state)) in intel_cdclk_update_crtc_min_cdclk()2949 return PTR_ERR(cdclk_state); in intel_cdclk_update_crtc_min_cdclk()2951 old_min_cdclk = cdclk_state->min_cdclk[crtc->pipe]; in intel_cdclk_update_crtc_min_cdclk()2959 cdclk_state->min_cdclk[crtc->pipe] = new_min_cdclk; in intel_cdclk_update_crtc_min_cdclk()2961 ret = intel_atomic_lock_global_state(&cdclk_state->base); in intel_cdclk_update_crtc_min_cdclk()2982 struct intel_cdclk_state *cdclk_state; in intel_cdclk_update_crtc_min_voltage_level() local[all …]
4218 const struct intel_cdclk_state *cdclk_state) in hsw_ips_linetime_wm() argument4228 intel_cdclk_logical(cdclk_state)); in hsw_ips_linetime_wm()4260 const struct intel_cdclk_state *cdclk_state; in hsw_compute_linetime_wm() local4270 cdclk_state = intel_atomic_get_cdclk_state(state); in hsw_compute_linetime_wm()4271 if (IS_ERR(cdclk_state)) in hsw_compute_linetime_wm()4272 return PTR_ERR(cdclk_state); in hsw_compute_linetime_wm()4275 cdclk_state); in hsw_compute_linetime_wm()