| /linux/drivers/gpu/drm/amd/display/amdgpu_dm/ |
| H A D | amdgpu_dm_backlight.c | 56 struct amdgpu_dm_backlight_caps *caps = &dm->backlight_caps[bl_idx]; in amdgpu_dm_update_backlight_caps()
58 if (caps->caps_valid) in amdgpu_dm_update_backlight_caps()
62 amdgpu_acpi_get_backlight_caps(caps); in amdgpu_dm_update_backlight_caps()
65 if (caps->caps_valid) { in amdgpu_dm_update_backlight_caps()
66 int spread = caps->max_input_signal - caps->min_input_signal; in amdgpu_dm_update_backlight_caps()
68 if (caps->max_input_signal > AMDGPU_DM_DEFAULT_MAX_BACKLIGHT || in amdgpu_dm_update_backlight_caps()
69 caps->min_input_signal < 0 || in amdgpu_dm_update_backlight_caps()
72 drm_dbg_kms(adev_to_drm(dm->adev), "DM: Invalid backlight caps: min=%d, max=%d\n", in amdgpu_dm_update_backlight_caps()
73 caps in amdgpu_dm_update_backlight_caps()
55 struct amdgpu_dm_backlight_caps *caps = &dm->backlight_caps[bl_idx]; amdgpu_dm_update_backlight_caps() local
90 get_brightness_range(const struct amdgpu_dm_backlight_caps * caps,unsigned int * min,unsigned int * max) get_brightness_range() argument
122 convert_custom_brightness(const struct amdgpu_dm_backlight_caps * caps,unsigned int min,unsigned int max,uint32_t * user_brightness) convert_custom_brightness() argument
189 convert_brightness_from_user(const struct amdgpu_dm_backlight_caps * caps,uint32_t brightness) convert_brightness_from_user() argument
206 convert_brightness_to_user(const struct amdgpu_dm_backlight_caps * caps,uint32_t brightness) convert_brightness_to_user() argument
260 struct amdgpu_dm_backlight_caps *caps; amdgpu_dm_backlight_set_level() local
369 struct amdgpu_dm_backlight_caps caps; amdgpu_dm_backlight_get_level() local
409 amdgpu_dm_backlight_fill_props(const struct amdgpu_dm_backlight_caps * caps,bool is_system_supplied,bool custom_curve_enabled,struct backlight_properties * props) amdgpu_dm_backlight_fill_props() argument
443 struct amdgpu_dm_backlight_caps *caps; amdgpu_dm_register_backlight_device() local
502 struct amdgpu_dm_backlight_caps *caps; amdgpu_dm_update_connector_ext_caps() local
[all...] |
| /linux/drivers/net/wireless/ath/ath5k/ |
| H A D | caps.c | 35 struct ath5k_capabilities *caps = &ah->ah_capabilities; in ath5k_hw_set_capabilities() local
39 ee_header = caps->cap_eeprom.ee_header; in ath5k_hw_set_capabilities()
46 caps->cap_range.range_5ghz_min = 5120; in ath5k_hw_set_capabilities()
47 caps->cap_range.range_5ghz_max = 5430; in ath5k_hw_set_capabilities()
48 caps->cap_range.range_2ghz_min = 0; in ath5k_hw_set_capabilities()
49 caps->cap_range.range_2ghz_max = 0; in ath5k_hw_set_capabilities()
52 __set_bit(AR5K_MODE_11A, caps->cap_mode); in ath5k_hw_set_capabilities()
69 if (ath_is_49ghz_allowed(caps->cap_eeprom.ee_regdomain)) in ath5k_hw_set_capabilities()
70 caps->cap_range.range_5ghz_min = 4920; in ath5k_hw_set_capabilities()
72 caps->cap_range.range_5ghz_min = 5005; in ath5k_hw_set_capabilities()
[all …]
|
| /linux/drivers/net/ethernet/netronome/nfp/ |
| H A D | nfp_net_ctrl.c | 12 static void nfp_net_tlv_caps_reset(struct nfp_net_tlv_caps *caps) in nfp_net_tlv_caps_reset() argument
14 memset(caps, 0, sizeof(*caps)); in nfp_net_tlv_caps_reset()
15 caps->me_freq_mhz = 1200; in nfp_net_tlv_caps_reset()
16 caps->mbox_off = NFP_NET_CFG_MBOX_BASE; in nfp_net_tlv_caps_reset()
17 caps->mbox_len = NFP_NET_CFG_MBOX_VAL_MAX_SZ; in nfp_net_tlv_caps_reset()
21 nfp_net_tls_parse_crypto_ops(struct device *dev, struct nfp_net_tlv_caps *caps, in nfp_net_tls_parse_crypto_ops() argument
27 if (caps->tls_resync_ss && !rx_stream_scan) in nfp_net_tls_parse_crypto_ops()
37 caps->crypto_ops = readl(data); in nfp_net_tls_parse_crypto_ops()
38 caps->crypto_enable_off = data - ctrl_mem + 16; in nfp_net_tls_parse_crypto_ops()
39 caps->tls_resync_ss = rx_stream_scan; in nfp_net_tls_parse_crypto_ops()
[all …]
|
| /linux/net/bluetooth/ |
| H A D | hci_codec.c | 12 void *caps, in hci_codec_list_add() argument
31 memcpy(entry->caps, caps, len); in hci_codec_list_add()
57 struct hci_codec_caps *caps; in hci_read_codec_capabilities() local
100 caps = (void *)skb->data; in hci_read_codec_capabilities()
101 if (skb->len < sizeof(*caps)) in hci_read_codec_capabilities()
103 if (skb->len < sizeof(caps->len) + caps->len) in hci_read_codec_capabilities()
105 len += sizeof(caps->len) + caps->len; in hci_read_codec_capabilities()
106 skb_pull(skb, sizeof(caps->len) + caps->len); in hci_read_codec_capabilities()
126 struct hci_op_read_local_codec_caps caps; in hci_read_supported_codecs() local
157 memset(&caps, 0, sizeof(caps)); in hci_read_supported_codecs()
[all …]
|
| /linux/drivers/net/ethernet/mellanox/mlx5/core/steering/sws/ |
| H A D | dr_domain.c | 9 ((dmn)->info.caps.dmn_type##_sw_owner || \
10 ((dmn)->info.caps.dmn_type##_sw_owner_v2 && \
11 (dmn)->info.caps.sw_format_ver <= MLX5_STEERING_FORMAT_CONNECTX_8))
15 return dmn->info.caps.sw_format_ver >= MLX5_STEERING_FORMAT_CONNECTX_6DX && in mlx5dr_domain_is_support_ptrn_arg()
16 dmn->info.caps.support_modify_argument; in mlx5dr_domain_is_support_ptrn_arg()
167 dmn->ste_ctx = mlx5dr_ste_get_ctx(dmn->info.caps.sw_format_ver); in dr_domain_init_resources()
230 struct mlx5dr_esw_caps *esw_caps = &dmn->info.caps.esw_caps; in dr_domain_fill_uplink_caps()
236 uplink_vport->vhca_gvmi = dmn->info.caps.gvmi; in dr_domain_fill_uplink_caps()
262 vport_caps->vhca_gvmi = dmn->info.caps.gvmi; in dr_domain_query_vport()
270 &dmn->info.caps.vports.esw_manager_caps); in dr_domain_query_esw_mgr()
[all …]
|
| H A D | dr_matcher.c | 109 dr_matcher_supp_vxlan_gpe(struct mlx5dr_cmd_caps *caps) in dr_matcher_supp_vxlan_gpe() argument
111 return (caps->sw_format_ver >= MLX5_STEERING_FORMAT_CONNECTX_6DX) || in dr_matcher_supp_vxlan_gpe()
112 (caps->flex_protocols & MLX5_FLEX_PARSER_VXLAN_GPE_ENABLED); in dr_matcher_supp_vxlan_gpe()
120 dr_matcher_supp_vxlan_gpe(&dmn->info.caps); in dr_mask_is_tnl_vxlan_gpe()
137 dr_matcher_supp_flex_parser_ok(struct mlx5dr_cmd_caps *caps) in dr_matcher_supp_flex_parser_ok() argument
139 return caps->flex_parser_ok_bits_supp; in dr_matcher_supp_flex_parser_ok()
145 return dr_matcher_supp_flex_parser_ok(&dmn->info.caps) && in dr_mask_is_tnl_geneve_tlv_opt_exist_set()
150 dr_matcher_supp_tnl_geneve(struct mlx5dr_cmd_caps *caps) in dr_matcher_supp_tnl_geneve() argument
152 return (caps->sw_format_ver >= MLX5_STEERING_FORMAT_CONNECTX_6DX) || in dr_matcher_supp_tnl_geneve()
153 (caps->flex_protocols & MLX5_FLEX_PARSER_GENEVE_ENABLED); in dr_matcher_supp_tnl_geneve()
[all …]
|
| /linux/arch/powerpc/perf/ |
| H A D | hv-common.c | 8 unsigned long hv_perf_caps_get(struct hv_perf_caps *caps) in hv_perf_caps_get() argument
13 struct hv_gpci_system_performance_capabilities caps; in hv_perf_caps_get() member
31 pr_devel("capability_mask: 0x%x\n", arg.caps.capability_mask); in hv_perf_caps_get()
33 caps->version = arg.params.counter_info_version_out; in hv_perf_caps_get()
34 caps->collect_privileged = !!arg.caps.perf_collect_privileged; in hv_perf_caps_get()
35 caps->ga = !!(arg.caps.capability_mask & HV_GPCI_CM_GA); in hv_perf_caps_get()
36 caps->expanded = !!(arg.caps.capability_mask & HV_GPCI_CM_EXPANDED); in hv_perf_caps_get()
37 caps->lab = !!(arg.caps.capability_mask & HV_GPCI_CM_LAB); in hv_perf_caps_get()
|
| /linux/tools/power/cpupower/utils/helpers/ |
| H A D | cpuid.c | 60 cpu_info->caps = 0; in get_cpu_info()
122 cpu_info->caps |= CPUPOWER_CAP_INV_TSC; in get_cpu_info()
126 cpu_info->caps |= CPUPOWER_CAP_APERF; in get_cpu_info()
133 cpu_info->caps |= CPUPOWER_CAP_AMD_CPB; in get_cpu_info()
136 cpu_info->caps |= CPUPOWER_CAP_AMD_CPB_MSR; in get_cpu_info()
142 cpu_info->caps |= CPUPOWER_CAP_AMD_HW_PSTATE; in get_cpu_info()
145 cpu_info->caps |= CPUPOWER_CAP_AMD_PSTATEDEF; in get_cpu_info()
151 cpu_info->caps |= CPUPOWER_CAP_AMD_RDPRU; in get_cpu_info()
154 cpu_info->caps |= CPUPOWER_CAP_AMD_PSTATE; in get_cpu_info()
160 cpu_info->caps &= ~CPUPOWER_CAP_AMD_CPB; in get_cpu_info()
[all …]
|
| /linux/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/ |
| H A D | context.c | 8 return IS_BIT_SET(ctx->caps->rtc_reparse_mode, MLX5_IFC_RTC_REPARSE_BY_STC); in mlx5hws_context_cap_dynamic_reparse()
37 max_log_sz = min(MLX5HWS_POOL_STC_LOG_SZ, ctx->caps->stc_alloc_log_max); in hws_context_pools_init()
38 pool_attr.alloc_log_sz = max(max_log_sz, ctx->caps->stc_alloc_log_gran); in hws_context_pools_init()
91 struct mlx5hws_cmd_query_caps *caps = ctx->caps; in hws_context_check_hws_supp() local
94 if (!caps->wqe_based_update) { in hws_context_check_hws_supp()
99 if (!caps->eswitch_manager) { in hws_context_check_hws_supp()
105 if ((!caps->nic_ft.reparse || in hws_context_check_hws_supp()
106 (!caps->fdb_ft.reparse && caps->eswitch_manager)) || in hws_context_check_hws_supp()
107 !IS_BIT_SET(caps->rtc_reparse_mode, MLX5_IFC_RTC_REPARSE_ALWAYS)) { in hws_context_check_hws_supp()
113 if (!IS_BIT_SET(caps->ste_format, MLX5_IFC_RTC_STE_FORMAT_8DW)) { in hws_context_check_hws_supp()
[all …]
|
| H A D | debug.c | 272 struct mlx5hws_cmd_query_caps *caps = ctx->caps; in hws_debug_dump_context_caps() local
277 caps->fw_ver, in hws_debug_dump_context_caps()
278 caps->wqe_based_update, in hws_debug_dump_context_caps()
279 caps->ste_format, in hws_debug_dump_context_caps()
280 caps->ste_alloc_log_max, in hws_debug_dump_context_caps()
281 caps->log_header_modify_argument_max_alloc); in hws_debug_dump_context_caps()
284 caps->flex_protocols, in hws_debug_dump_context_caps()
285 caps->rtc_reparse_mode, in hws_debug_dump_context_caps()
286 caps->rtc_index_mode, in hws_debug_dump_context_caps()
287 caps->ste_alloc_log_gran, in hws_debug_dump_context_caps()
[all …]
|
| /linux/drivers/gpu/drm/arm/display/komeda/ |
| H A D | komeda_format_caps.c | 16 const struct komeda_format_caps *caps; in komeda_get_format_caps() local
22 caps = &table->format_caps[id]; in komeda_get_format_caps()
24 if (fourcc != caps->fourcc) in komeda_get_format_caps()
27 if ((modifier == 0ULL) && (caps->supported_afbc_layouts == 0)) in komeda_get_format_caps()
28 return caps; in komeda_get_format_caps()
30 if (has_bits(afbc_features, caps->supported_afbc_features) && in komeda_get_format_caps()
31 has_bit(afbc_layout, caps->supported_afbc_layouts)) in komeda_get_format_caps()
32 return caps; in komeda_get_format_caps()
99 const struct komeda_format_caps *caps; in komeda_format_mod_supported() local
101 caps = komeda_get_format_caps(table, fourcc, modifier); in komeda_format_mod_supported()
[all …]
|
| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn42b/ |
| H A D | dcn42b_resource.c | 892 ctx->dc->caps.extended_aux_timeout_support); in dcn42b_aux_engine_create()
1900 return dc->caps.max_cursor_size; in dcn42b_get_max_hw_cursor_size()
1986 dc->caps.ips_v2_support = true; in dcn42b_resource_construct()
1987 dc->caps.max_downscale_ratio = 600; in dcn42b_resource_construct()
1988 dc->caps.i2c_speed_in_khz = 100; in dcn42b_resource_construct()
1989 dc->caps.i2c_speed_in_khz_hdcp = 100; /*1.4 w/a applied by default*/ in dcn42b_resource_construct()
1991 dc->caps.max_cursor_size = 64; in dcn42b_resource_construct()
1992 dc->caps.max_buffered_cursor_size = 64; in dcn42b_resource_construct()
1993 dc->caps.cursor_not_scaled = true; in dcn42b_resource_construct()
1994 dc->caps.min_horizontal_blanking_period = 80; in dcn42b_resource_construct()
[all …]
|
| /linux/drivers/mtd/nand/ |
| H A D | ecc-mtk.c | 60 const struct mtk_ecc_caps *caps; member
148 dec = readw(ecc->regs + ecc->caps->ecc_regs[ECC_DECIRQ_STA]) in mtk_ecc_irq()
151 dec = readw(ecc->regs + ecc->caps->ecc_regs[ECC_DECDONE]); in mtk_ecc_irq()
157 readw(ecc->regs + ecc->caps->ecc_regs[ECC_DECIRQ_STA]); in mtk_ecc_irq()
164 enc = readl(ecc->regs + ecc->caps->ecc_regs[ECC_ENCIRQ_STA]) in mtk_ecc_irq()
180 for (i = 0; i < ecc->caps->num_ecc_strength; i++) { in mtk_ecc_config()
181 if (ecc->caps->ecc_strength[i] == config->strength) in mtk_ecc_config()
185 if (i == ecc->caps->num_ecc_strength) { in mtk_ecc_config()
197 reg = ecc_bit | (config->mode << ecc->caps->ecc_mode_shift); in mtk_ecc_config()
208 config->strength * ecc->caps->parity_bits; in mtk_ecc_config()
[all …]
|
| /linux/drivers/net/wireless/morsemicro/mm81x/ |
| H A D | rc.c | 68 struct mmrc_sta_capabilities *caps) in mm81x_rc_sta_config_guard_per_bw() argument
70 caps->guard = BIT(MMRC_GUARD_LONG); in mm81x_rc_sta_config_guard_per_bw()
72 if (caps->bandwidth & BIT(MMRC_BW_1MHZ)) { in mm81x_rc_sta_config_guard_per_bw()
73 caps->sgi_per_bw |= SGI_PER_BW(MMRC_BW_1MHZ); in mm81x_rc_sta_config_guard_per_bw()
74 caps->guard |= BIT(MMRC_GUARD_SHORT); in mm81x_rc_sta_config_guard_per_bw()
77 if (caps->bandwidth & BIT(MMRC_BW_2MHZ)) { in mm81x_rc_sta_config_guard_per_bw()
78 caps->sgi_per_bw |= SGI_PER_BW(MMRC_BW_2MHZ); in mm81x_rc_sta_config_guard_per_bw()
79 caps->guard |= BIT(MMRC_GUARD_SHORT); in mm81x_rc_sta_config_guard_per_bw()
82 if (caps->bandwidth & BIT(MMRC_BW_4MHZ)) { in mm81x_rc_sta_config_guard_per_bw()
83 caps->sgi_per_bw |= SGI_PER_BW(MMRC_BW_4MHZ); in mm81x_rc_sta_config_guard_per_bw()
[all …]
|
| /linux/drivers/vfio/pci/ |
| H A D | vfio_pci_zdev.c | 23 static int zpci_base_cap(struct zpci_dev *zdev, struct vfio_info_cap *caps) in zpci_base_cap() argument
39 return vfio_info_add_capability(caps, &cap.header, sizeof(cap)); in zpci_base_cap()
45 static int zpci_group_cap(struct zpci_dev *zdev, struct vfio_info_cap *caps) in zpci_group_cap() argument
61 return vfio_info_add_capability(caps, &cap.header, sizeof(cap)); in zpci_group_cap()
67 static int zpci_util_cap(struct zpci_dev *zdev, struct vfio_info_cap *caps) in zpci_util_cap() argument
82 ret = vfio_info_add_capability(caps, &cap->header, cap_size); in zpci_util_cap()
92 static int zpci_pfip_cap(struct zpci_dev *zdev, struct vfio_info_cap *caps) in zpci_pfip_cap() argument
107 ret = vfio_info_add_capability(caps, &cap->header, cap_size); in zpci_pfip_cap()
118 struct vfio_info_cap *caps) in vfio_pci_info_zdev_add_caps() argument
126 ret = zpci_base_cap(zdev, caps); in vfio_pci_info_zdev_add_caps()
[all …]
|
| /linux/drivers/mmc/core/ |
| H A D | host.c | 283 host->caps |= MMC_CAP_8_BIT_DATA; in mmc_of_parse()
286 host->caps |= MMC_CAP_4_BIT_DATA; in mmc_of_parse()
316 host->caps |= MMC_CAP_NONREMOVABLE; in mmc_of_parse()
326 host->caps |= MMC_CAP_NEEDS_POLL; in mmc_of_parse()
351 host->caps |= MMC_CAP_SD_HIGHSPEED; in mmc_of_parse()
353 host->caps |= MMC_CAP_MMC_HIGHSPEED; in mmc_of_parse()
355 host->caps |= MMC_CAP_UHS_SDR12; in mmc_of_parse()
357 host->caps |= MMC_CAP_UHS_SDR25; in mmc_of_parse()
359 host->caps |= MMC_CAP_UHS_SDR50; in mmc_of_parse()
361 host->caps |= MMC_CAP_UHS_SDR104; in mmc_of_parse()
[all …]
|
| /linux/drivers/gpu/drm/amd/display/dc/dcn20/ |
| H A D | dcn20_dwb.c | 50 static bool dwb2_get_caps(struct dwbc *dwbc, struct dwb_caps *caps) in dwb2_get_caps() argument
53 if (caps) { in dwb2_get_caps()
54 caps->adapter_id = 0; /* we only support 1 adapter currently */ in dwb2_get_caps()
55 caps->hw_version = DCN_VERSION_2_0; in dwb2_get_caps()
56 caps->num_pipes = 1; in dwb2_get_caps()
57 memset(&caps->reserved, 0, sizeof(caps->reserved)); in dwb2_get_caps()
58 memset(&caps->reserved2, 0, sizeof(caps->reserved2)); in dwb2_get_caps()
59 caps->sw_version = dwb_ver_1_0; in dwb2_get_caps()
60 caps->caps.support_dwb = true; in dwb2_get_caps()
61 caps->caps.support_ogam = false; in dwb2_get_caps()
[all …]
|
| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn42/ |
| H A D | dcn42_resource.c | 839 ctx->dc->caps.extended_aux_timeout_support); in dcn42_aux_engine_create()
1914 return dc->caps.max_cursor_size; in dcn42_get_max_hw_cursor_size()
2022 dc->caps.ips_v2_support = true; in dcn42_resource_construct()
2023 dc->caps.max_downscale_ratio = 600; in dcn42_resource_construct()
2024 dc->caps.i2c_speed_in_khz = 100; in dcn42_resource_construct()
2025 dc->caps.i2c_speed_in_khz_hdcp = 100; /*1.4 w/a applied by default*/ in dcn42_resource_construct()
2027 dc->caps.max_cursor_size = 64; in dcn42_resource_construct()
2028 dc->caps.max_buffered_cursor_size = 64; in dcn42_resource_construct()
2029 dc->caps.cursor_not_scaled = true; in dcn42_resource_construct()
2030 dc->caps.min_horizontal_blanking_period = 80; in dcn42_resource_construct()
[all …]
|
| /linux/include/linux/mlx5/ |
| H A D | device.h | 1298 MLX5_GET(cmd_hca_cap, mdev->caps.hca[MLX5_CAP_GENERAL]->cur, cap)
1301 MLX5_GET64(cmd_hca_cap, mdev->caps.hca[MLX5_CAP_GENERAL]->cur, cap)
1304 MLX5_GET(cmd_hca_cap, mdev->caps.hca[MLX5_CAP_GENERAL]->max, cap)
1307 MLX5_GET(cmd_hca_cap_2, mdev->caps.hca[MLX5_CAP_GENERAL_2]->cur, cap)
1310 MLX5_GET64(cmd_hca_cap_2, mdev->caps.hca[MLX5_CAP_GENERAL_2]->cur, cap)
1313 MLX5_GET(cmd_hca_cap_2, mdev->caps.hca[MLX5_CAP_GENERAL_2]->max, cap)
1317 mdev->caps.hca[MLX5_CAP_ETHERNET_OFFLOADS]->cur, cap)
1321 mdev->caps.hca[MLX5_CAP_IPOIB_ENHANCED_OFFLOADS]->cur, cap)
1324 MLX5_GET(roce_cap, mdev->caps.hca[MLX5_CAP_ROCE]->cur, cap)
1327 MLX5_GET(roce_cap, mdev->caps.hca[MLX5_CAP_ROCE]->max, cap)
[all …]
|
| /linux/sound/soc/codecs/ |
| H A D | mt6359-accdet.c | 81 if (priv->caps & ACCDET_PMIC_EINT0) { in adjust_eint_analog_setting()
87 } else if (priv->caps & ACCDET_PMIC_EINT1) { in adjust_eint_analog_setting()
108 if (priv->caps & ACCDET_PMIC_EINT0) { in adjust_eint_digital_setting()
113 } else if (priv->caps & ACCDET_PMIC_EINT1) { in adjust_eint_digital_setting()
121 if (priv->caps & ACCDET_PMIC_EINT0) { in adjust_eint_digital_setting()
126 } else if (priv->caps & ACCDET_PMIC_EINT1) { in adjust_eint_digital_setting()
163 if (priv->caps & ACCDET_PMIC_EINT0) { in recover_eint_analog_setting()
168 } else if (priv->caps & ACCDET_PMIC_EINT1) { in recover_eint_analog_setting()
181 if (priv->caps & ACCDET_PMIC_EINT0) { in recover_eint_digital_setting()
185 } else if (priv->caps in recover_eint_digital_setting()
[all...] |
| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn303/ |
| H A D | dcn303_resource.c | 874 &aux_engine_regs[inst], &aux_mask, &aux_shift, ctx->dc->caps.extended_aux_timeout_support); in dcn303_aux_engine_create()
1308 dc->caps.max_downscale_ratio = 600; in dcn303_resource_construct()
1309 dc->caps.i2c_speed_in_khz = 100; in dcn303_resource_construct()
1310 dc->caps.i2c_speed_in_khz_hdcp = 5; /*1.4 w/a applied by derfault*/ in dcn303_resource_construct()
1311 dc->caps.max_cursor_size = 256; in dcn303_resource_construct()
1312 dc->caps.min_horizontal_blanking_period = 80; in dcn303_resource_construct()
1313 dc->caps.dmdata_alloc_size = 2048; in dcn303_resource_construct()
1314 dc->caps.mall_size_per_mem_channel = 4; in dcn303_resource_construct()
1316 dc->caps.mall_size_total = dc->caps.mall_size_per_mem_channel * in dcn303_resource_construct()
1319 dc->caps.cursor_cache_size = in dcn303_resource_construct()
[all …]
|
| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn302/ |
| H A D | dcn302_resource.c | 916 &aux_engine_regs[inst], &aux_mask, &aux_shift, ctx->dc->caps.extended_aux_timeout_support); in dcn302_aux_engine_create()
1367 dc->caps.max_downscale_ratio = 600; in dcn302_resource_construct()
1368 dc->caps.i2c_speed_in_khz = 100; in dcn302_resource_construct()
1369 dc->caps.i2c_speed_in_khz_hdcp = 5; /*1.4 w/a applied by derfault*/ in dcn302_resource_construct()
1370 dc->caps.max_cursor_size = 256; in dcn302_resource_construct()
1371 dc->caps.min_horizontal_blanking_period = 80; in dcn302_resource_construct()
1372 dc->caps.dmdata_alloc_size = 2048; in dcn302_resource_construct()
1373 dc->caps.mall_size_per_mem_channel = 4; in dcn302_resource_construct()
1375 …dc->caps.mall_size_total = dc->caps.mall_size_per_mem_channel * dc->ctx->dc_bios->vram_info.num_ch… in dcn302_resource_construct()
1376 dc->caps.cursor_cache_size = dc->caps.max_cursor_size * dc->caps.max_cursor_size * 8; in dcn302_resource_construct()
[all …]
|
| /linux/tools/testing/selftests/clone3/ |
| H A D | clone3_cap_checkpoint_restore.c | 93 cap_t caps;
95 caps = cap_get_proc(); in set_capability()
96 if (!caps) { in set_capability()
102 if (cap_clear(caps)) { in set_capability()
107 cap_set_flag(caps, CAP_EFFECTIVE, 3, cap_values, CAP_SET); in set_capability()
108 cap_set_flag(caps, CAP_PERMITTED, 3, cap_values, CAP_SET); in set_capability()
110 if (cap_set_proc(caps)) { in set_capability()
116 if (cap_free(caps)) in set_capability()
100 cap_t caps; set_capability() local
|
| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn321/ |
| H A D | dcn321_resource.c | 817 ctx->dc->caps.extended_aux_timeout_support); in dcn321_aux_engine_create()
1867 dc->caps.max_downscale_ratio = 600; in dcn321_resource_construct()
1868 dc->caps.i2c_speed_in_khz = 100; in dcn321_resource_construct()
1869 dc->caps.i2c_speed_in_khz_hdcp = 100; /*1.4 w/a applied by default*/ in dcn321_resource_construct()
1871 dc->caps.max_cursor_size = 64; in dcn321_resource_construct()
1872 dc->caps.max_buffered_cursor_size = 64; // sqrt(16 * 1024 / 4) in dcn321_resource_construct()
1873 dc->caps.min_horizontal_blanking_period = 80; in dcn321_resource_construct()
1874 dc->caps.dmdata_alloc_size = 2048; in dcn321_resource_construct()
1875 dc->caps.mall_size_per_mem_channel = 4; in dcn321_resource_construct()
1877 …dc->caps.mall_size_total = dc->caps.mall_size_per_mem_channel * dc->ctx->dc_bios->vram_info.num_ch… in dcn321_resource_construct()
[all …]
|
| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn401/ |
| H A D | dcn401_resource.c | 835 ctx->dc->caps.extended_aux_timeout_support); in dcn401_aux_engine_create()
1786 dc->caps.max_cab_allocation_bytes = dcn401_calc_num_avail_chans_for_mall( in dcn401_update_bw_bounding_box_fpu()
1788 dc->caps.mall_size_per_mem_channel * 1024 * 1024; in dcn401_update_bw_bounding_box_fpu()
1789 dc->caps.mall_size_total = dc->caps.max_cab_allocation_bytes; in dcn401_update_bw_bounding_box_fpu()
2071 dc->caps.max_downscale_ratio = 600; in dcn401_resource_construct()
2072 dc->caps.i2c_speed_in_khz = 95; in dcn401_resource_construct()
2073 dc->caps.i2c_speed_in_khz_hdcp = 95; /*1.4 w/a applied by default*/ in dcn401_resource_construct()
2075 dc->caps.max_cursor_size = 64; in dcn401_resource_construct()
2076 dc->caps.max_buffered_cursor_size = 64; in dcn401_resource_construct()
2077 dc->caps.cursor_not_scaled = true; in dcn401_resource_construct()
[all …]
|