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Searched refs:caps (Results 1 – 25 of 974) sorted by relevance

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/linux/drivers/net/wireless/ath/ath5k/
H A Dcaps.c35 struct ath5k_capabilities *caps = &ah->ah_capabilities; in ath5k_hw_set_capabilities() local
39 ee_header = caps->cap_eeprom.ee_header; in ath5k_hw_set_capabilities()
46 caps->cap_range.range_5ghz_min = 5120; in ath5k_hw_set_capabilities()
47 caps->cap_range.range_5ghz_max = 5430; in ath5k_hw_set_capabilities()
48 caps->cap_range.range_2ghz_min = 0; in ath5k_hw_set_capabilities()
49 caps->cap_range.range_2ghz_max = 0; in ath5k_hw_set_capabilities()
52 __set_bit(AR5K_MODE_11A, caps->cap_mode); in ath5k_hw_set_capabilities()
69 if (ath_is_49ghz_allowed(caps->cap_eeprom.ee_regdomain)) in ath5k_hw_set_capabilities()
70 caps->cap_range.range_5ghz_min = 4920; in ath5k_hw_set_capabilities()
72 caps->cap_range.range_5ghz_min = 5005; in ath5k_hw_set_capabilities()
[all …]
/linux/drivers/net/ethernet/netronome/nfp/
H A Dnfp_net_ctrl.c12 static void nfp_net_tlv_caps_reset(struct nfp_net_tlv_caps *caps) in nfp_net_tlv_caps_reset() argument
14 memset(caps, 0, sizeof(*caps)); in nfp_net_tlv_caps_reset()
15 caps->me_freq_mhz = 1200; in nfp_net_tlv_caps_reset()
16 caps->mbox_off = NFP_NET_CFG_MBOX_BASE; in nfp_net_tlv_caps_reset()
17 caps->mbox_len = NFP_NET_CFG_MBOX_VAL_MAX_SZ; in nfp_net_tlv_caps_reset()
21 nfp_net_tls_parse_crypto_ops(struct device *dev, struct nfp_net_tlv_caps *caps, in nfp_net_tls_parse_crypto_ops() argument
27 if (caps->tls_resync_ss && !rx_stream_scan) in nfp_net_tls_parse_crypto_ops()
37 caps->crypto_ops = readl(data); in nfp_net_tls_parse_crypto_ops()
38 caps->crypto_enable_off = data - ctrl_mem + 16; in nfp_net_tls_parse_crypto_ops()
39 caps->tls_resync_ss = rx_stream_scan; in nfp_net_tls_parse_crypto_ops()
[all …]
/linux/drivers/net/ethernet/mellanox/mlx4/
H A Dmain.c299 dev->caps.reserved_uars = in mlx4_set_num_reserved_uars()
311 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP)) { in mlx4_check_port_params()
312 for (i = 0; i < dev->caps.num_ports - 1; i++) { in mlx4_check_port_params()
320 for (i = 0; i < dev->caps.num_ports; i++) { in mlx4_check_port_params()
321 if (!(port_type[i] & dev->caps.supported_type[i+1])) { in mlx4_check_port_params()
334 for (i = 1; i <= dev->caps.num_ports; ++i) in mlx4_set_port_mask()
335 dev->caps.port_mask[i] = dev->caps.port_type[i]; in mlx4_set_port_mask()
347 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS) { in mlx4_query_func()
363 struct mlx4_caps *dev_cap = &dev->caps; in mlx4_enable_cqe_eqe_stride()
399 dev->caps.vl_cap[port] = port_cap->max_vl; in _mlx4_dev_port()
[all …]
/linux/net/bluetooth/
H A Dhci_codec.c12 void *caps, in hci_codec_list_add() argument
31 memcpy(entry->caps, caps, len); in hci_codec_list_add()
57 struct hci_codec_caps *caps; in hci_read_codec_capabilities() local
100 caps = (void *)skb->data; in hci_read_codec_capabilities()
101 if (skb->len < sizeof(*caps)) in hci_read_codec_capabilities()
103 if (skb->len < caps->len) in hci_read_codec_capabilities()
105 len += sizeof(caps->len) + caps->len; in hci_read_codec_capabilities()
106 skb_pull(skb, sizeof(caps->len) + caps->len); in hci_read_codec_capabilities()
126 struct hci_op_read_local_codec_caps caps; in hci_read_supported_codecs() local
156 memset(&caps, 0, sizeof(caps)); in hci_read_supported_codecs()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dcn10/
H A Ddcn10_dwb.c45 static bool dwb1_get_caps(struct dwbc *dwbc, struct dwb_caps *caps) in dwb1_get_caps() argument
47 if (caps) { in dwb1_get_caps()
48 caps->adapter_id = 0; /* we only support 1 adapter currently */ in dwb1_get_caps()
49 caps->hw_version = DCN_VERSION_1_0; in dwb1_get_caps()
50 caps->num_pipes = 2; in dwb1_get_caps()
51 memset(&caps->reserved, 0, sizeof(caps->reserved)); in dwb1_get_caps()
52 memset(&caps->reserved2, 0, sizeof(caps->reserved2)); in dwb1_get_caps()
53 caps->sw_version = dwb_ver_1_0; in dwb1_get_caps()
54 caps->caps.support_dwb = true; in dwb1_get_caps()
55 caps->caps.support_ogam = false; in dwb1_get_caps()
[all …]
/linux/drivers/net/ethernet/mellanox/mlx5/core/steering/sws/
H A Ddr_domain.c9 ((dmn)->info.caps.dmn_type##_sw_owner || \
10 ((dmn)->info.caps.dmn_type##_sw_owner_v2 && \
11 (dmn)->info.caps.sw_format_ver <= MLX5_STEERING_FORMAT_CONNECTX_8))
15 return dmn->info.caps.sw_format_ver >= MLX5_STEERING_FORMAT_CONNECTX_6DX && in mlx5dr_domain_is_support_ptrn_arg()
16 dmn->info.caps.support_modify_argument; in mlx5dr_domain_is_support_ptrn_arg()
167 dmn->ste_ctx = mlx5dr_ste_get_ctx(dmn->info.caps.sw_format_ver); in dr_domain_init_resources()
230 struct mlx5dr_esw_caps *esw_caps = &dmn->info.caps.esw_caps; in dr_domain_fill_uplink_caps()
236 uplink_vport->vhca_gvmi = dmn->info.caps.gvmi; in dr_domain_fill_uplink_caps()
262 vport_caps->vhca_gvmi = dmn->info.caps.gvmi; in dr_domain_query_vport()
270 &dmn->info.caps.vports.esw_manager_caps); in dr_domain_query_esw_mgr()
[all …]
H A Ddr_matcher.c109 dr_matcher_supp_vxlan_gpe(struct mlx5dr_cmd_caps *caps) in dr_matcher_supp_vxlan_gpe() argument
111 return (caps->sw_format_ver >= MLX5_STEERING_FORMAT_CONNECTX_6DX) || in dr_matcher_supp_vxlan_gpe()
112 (caps->flex_protocols & MLX5_FLEX_PARSER_VXLAN_GPE_ENABLED); in dr_matcher_supp_vxlan_gpe()
120 dr_matcher_supp_vxlan_gpe(&dmn->info.caps); in dr_mask_is_tnl_vxlan_gpe()
137 dr_matcher_supp_flex_parser_ok(struct mlx5dr_cmd_caps *caps) in dr_matcher_supp_flex_parser_ok() argument
139 return caps->flex_parser_ok_bits_supp; in dr_matcher_supp_flex_parser_ok()
145 return dr_matcher_supp_flex_parser_ok(&dmn->info.caps) && in dr_mask_is_tnl_geneve_tlv_opt_exist_set()
150 dr_matcher_supp_tnl_geneve(struct mlx5dr_cmd_caps *caps) in dr_matcher_supp_tnl_geneve() argument
152 return (caps->sw_format_ver >= MLX5_STEERING_FORMAT_CONNECTX_6DX) || in dr_matcher_supp_tnl_geneve()
153 (caps->flex_protocols & MLX5_FLEX_PARSER_GENEVE_ENABLED); in dr_matcher_supp_tnl_geneve()
[all …]
/linux/drivers/infiniband/hw/hns/
H A Dhns_roce_main.c70 if (port >= hr_dev->caps.num_ports) in hns_roce_add_gid()
84 if (port >= hr_dev->caps.num_ports) in hns_roce_del_gid()
103 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_BOND) { in hns_roce_get_port_state()
183 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_BOND) { in hns_roce_netdev_event()
189 for (port = 0; port < hr_dev->caps.num_ports; port++) { in hns_roce_netdev_event()
208 for (i = 0; i < hr_dev->caps.num_ports; i++) { in hns_roce_setup_mtu_mac()
226 props->fw_ver = hr_dev->caps.fw_ver; in hns_roce_query_device()
229 props->page_size_cap = hr_dev->caps.page_size_cap; in hns_roce_query_device()
233 props->max_qp = hr_dev->caps.num_qps; in hns_roce_query_device()
234 props->max_qp_wr = hr_dev->caps.max_wqes; in hns_roce_query_device()
[all …]
H A Dhns_roce_hw_v2.c1907 hr_dev->caps.fw_ver = (u64)(le32_to_cpu(resp->fw_ver)); in hns_roce_query_fw_ver()
1947 if (port > hr_dev->caps.num_ports) in hns_roce_hw_v2_query_counter()
2011 struct hns_roce_caps *caps = &hr_dev->caps; in load_func_res_caps() local
2032 caps->qpc_bt_num = hr_reg_read(r_a, FUNC_RES_A_QPC_BT_NUM) / func_num; in load_func_res_caps()
2033 caps->srqc_bt_num = hr_reg_read(r_a, FUNC_RES_A_SRQC_BT_NUM) / func_num; in load_func_res_caps()
2034 caps->cqc_bt_num = hr_reg_read(r_a, FUNC_RES_A_CQC_BT_NUM) / func_num; in load_func_res_caps()
2035 caps->mpt_bt_num = hr_reg_read(r_a, FUNC_RES_A_MPT_BT_NUM) / func_num; in load_func_res_caps()
2036 caps->eqc_bt_num = hr_reg_read(r_a, FUNC_RES_A_EQC_BT_NUM) / func_num; in load_func_res_caps()
2037 caps->smac_bt_num = hr_reg_read(r_b, FUNC_RES_B_SMAC_NUM) / func_num; in load_func_res_caps()
2038 caps->sgid_bt_num = hr_reg_read(r_b, FUNC_RES_B_SGID_NUM) / func_num; in load_func_res_caps()
[all …]
/linux/tools/power/cpupower/utils/helpers/
H A Dcpuid.c60 cpu_info->caps = 0; in get_cpu_info()
122 cpu_info->caps |= CPUPOWER_CAP_INV_TSC; in get_cpu_info()
126 cpu_info->caps |= CPUPOWER_CAP_APERF; in get_cpu_info()
133 cpu_info->caps |= CPUPOWER_CAP_AMD_CPB; in get_cpu_info()
136 cpu_info->caps |= CPUPOWER_CAP_AMD_CPB_MSR; in get_cpu_info()
142 cpu_info->caps |= CPUPOWER_CAP_AMD_HW_PSTATE; in get_cpu_info()
145 cpu_info->caps |= CPUPOWER_CAP_AMD_PSTATEDEF; in get_cpu_info()
151 cpu_info->caps |= CPUPOWER_CAP_AMD_RDPRU; in get_cpu_info()
154 cpu_info->caps |= CPUPOWER_CAP_AMD_PSTATE; in get_cpu_info()
160 cpu_info->caps &= ~CPUPOWER_CAP_AMD_CPB; in get_cpu_info()
[all …]
/linux/arch/powerpc/perf/
H A Dhv-common.c8 unsigned long hv_perf_caps_get(struct hv_perf_caps *caps) in hv_perf_caps_get() argument
13 struct hv_gpci_system_performance_capabilities caps; in hv_perf_caps_get() member
31 pr_devel("capability_mask: 0x%x\n", arg.caps.capability_mask); in hv_perf_caps_get()
33 caps->version = arg.params.counter_info_version_out; in hv_perf_caps_get()
34 caps->collect_privileged = !!arg.caps.perf_collect_privileged; in hv_perf_caps_get()
35 caps->ga = !!(arg.caps.capability_mask & HV_GPCI_CM_GA); in hv_perf_caps_get()
36 caps->expanded = !!(arg.caps.capability_mask & HV_GPCI_CM_EXPANDED); in hv_perf_caps_get()
37 caps->lab = !!(arg.caps.capability_mask & HV_GPCI_CM_LAB); in hv_perf_caps_get()
/linux/arch/powerpc/platforms/pseries/
H A Dvas-sysfs.c23 struct vas_cop_feat_caps *caps; member
32 static ssize_t update_total_credits_store(struct vas_cop_feat_caps *caps, in update_total_credits_store() argument
48 err = vas_reconfig_capabilties(caps->win_type, creds); in update_total_credits_store()
59 static ssize_t _name##_show(struct vas_cop_feat_caps *caps, char *buf) \
61 return sprintf(buf, "%d\n", atomic_read(&caps->_name)); \
125 struct vas_cop_feat_caps *caps; in vas_type_show() local
129 caps = centry->caps; in vas_type_show()
135 return entry->show(caps, buf); in vas_type_show()
142 struct vas_cop_feat_caps *caps; in vas_type_store() local
146 caps = centry->caps; in vas_type_store()
[all …]
H A Dvas.c323 struct vas_caps *caps; in vas_allocate_window() local
356 caps = &vascaps[VAS_GZIP_QOS_FEAT_TYPE]; in vas_allocate_window()
358 caps = &vascaps[VAS_GZIP_DEF_FEAT_TYPE]; in vas_allocate_window()
360 cop_feat_caps = &caps->caps; in vas_allocate_window()
414 caps->nr_open_wins_progress++; in vas_allocate_window()
450 if (!caps->nr_close_wins && !migration_in_progress) { in vas_allocate_window()
451 list_add(&txwin->win_list, &caps->list); in vas_allocate_window()
452 caps->nr_open_windows++; in vas_allocate_window()
453 caps->nr_open_wins_progress--; in vas_allocate_window()
475 caps->nr_open_wins_progress--; in vas_allocate_window()
[all …]
/linux/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/
H A Dcontext.c8 return IS_BIT_SET(ctx->caps->rtc_reparse_mode, MLX5_IFC_RTC_REPARSE_BY_STC); in mlx5hws_context_cap_dynamic_reparse()
37 max_log_sz = min(MLX5HWS_POOL_STC_LOG_SZ, ctx->caps->stc_alloc_log_max); in hws_context_pools_init()
38 pool_attr.alloc_log_sz = max(max_log_sz, ctx->caps->stc_alloc_log_gran); in hws_context_pools_init()
91 struct mlx5hws_cmd_query_caps *caps = ctx->caps; in hws_context_check_hws_supp() local
94 if (!caps->wqe_based_update) { in hws_context_check_hws_supp()
99 if (!caps->eswitch_manager) { in hws_context_check_hws_supp()
105 if ((!caps->nic_ft.reparse || in hws_context_check_hws_supp()
106 (!caps->fdb_ft.reparse && caps->eswitch_manager)) || in hws_context_check_hws_supp()
107 !IS_BIT_SET(caps->rtc_reparse_mode, MLX5_IFC_RTC_REPARSE_ALWAYS)) { in hws_context_check_hws_supp()
113 if (!IS_BIT_SET(caps->ste_format, MLX5_IFC_RTC_STE_FORMAT_8DW)) { in hws_context_check_hws_supp()
[all …]
H A Ddebug.c272 struct mlx5hws_cmd_query_caps *caps = ctx->caps; in hws_debug_dump_context_caps() local
277 caps->fw_ver, in hws_debug_dump_context_caps()
278 caps->wqe_based_update, in hws_debug_dump_context_caps()
279 caps->ste_format, in hws_debug_dump_context_caps()
280 caps->ste_alloc_log_max, in hws_debug_dump_context_caps()
281 caps->log_header_modify_argument_max_alloc); in hws_debug_dump_context_caps()
284 caps->flex_protocols, in hws_debug_dump_context_caps()
285 caps->rtc_reparse_mode, in hws_debug_dump_context_caps()
286 caps->rtc_index_mode, in hws_debug_dump_context_caps()
287 caps->ste_alloc_log_gran, in hws_debug_dump_context_caps()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dwb/dcn30/
H A Ddcn30_dwb.c46 static bool dwb3_get_caps(struct dwbc *dwbc, struct dwb_caps *caps) in dwb3_get_caps() argument
48 if (caps) { in dwb3_get_caps()
49 caps->adapter_id = 0; /* we only support 1 adapter currently */ in dwb3_get_caps()
50 caps->hw_version = DCN_VERSION_3_0; in dwb3_get_caps()
51 caps->num_pipes = 2; in dwb3_get_caps()
52 memset(&caps->reserved, 0, sizeof(caps->reserved)); in dwb3_get_caps()
53 memset(&caps->reserved2, 0, sizeof(caps->reserved2)); in dwb3_get_caps()
54 caps->sw_version = dwb_ver_2_0; in dwb3_get_caps()
55 caps->caps.support_dwb = true; in dwb3_get_caps()
56 caps->caps.support_ogam = true; in dwb3_get_caps()
[all …]
/linux/drivers/gpu/drm/omapdrm/
H A Domap_overlay.c29 u32 caps, u32 fourcc) in omap_plane_find_free_overlay() argument
34 DBG("caps: %x fourcc: %x", caps, fourcc); in omap_plane_find_free_overlay()
40 cur->idx, cur->id, cur->caps); in omap_plane_find_free_overlay()
47 if (caps & ~cur->caps) in omap_plane_find_free_overlay()
70 u32 caps, u32 fourcc, struct omap_hw_overlay **overlay, in omap_overlay_assign() argument
78 ovl = omap_plane_find_free_overlay(s->dev, overlay_map, caps, fourcc); in omap_overlay_assign()
87 caps, fourcc); in omap_overlay_assign()
98 DBG("%s: assign to plane %s caps %x", ovl->name, plane->name, caps); in omap_overlay_assign()
102 r_ovl->name, plane->name, caps); in omap_overlay_assign()
158 enum omap_overlay_caps caps) in omap_overlay_init() argument
[all …]
/linux/drivers/gpu/drm/msm/disp/mdp5/
H A Dmdp5_pipe.c10 uint32_t caps, uint32_t blkcfg, in mdp5_pipe_assign() argument
45 if (caps & ~cur->caps) in mdp5_pipe_assign()
52 if (cur->caps & MDP_PIPE_CAP_CURSOR && in mdp5_pipe_assign()
59 if (!(*hwpipe) || (hweight_long(cur->caps & ~caps) < in mdp5_pipe_assign()
60 hweight_long((*hwpipe)->caps & ~caps))) { in mdp5_pipe_assign()
70 if (r_cur->caps != cur->caps) in mdp5_pipe_assign()
110 (*hwpipe)->name, plane->name, caps); in mdp5_pipe_assign()
115 (*r_hwpipe)->name, plane->name, caps); in mdp5_pipe_assign()
156 uint32_t reg_offset, uint32_t caps) in mdp5_pipe_init() argument
167 hwpipe->caps = caps; in mdp5_pipe_init()
/linux/drivers/gpu/drm/arm/display/komeda/
H A Dkomeda_format_caps.c16 const struct komeda_format_caps *caps; in komeda_get_format_caps() local
22 caps = &table->format_caps[id]; in komeda_get_format_caps()
24 if (fourcc != caps->fourcc) in komeda_get_format_caps()
27 if ((modifier == 0ULL) && (caps->supported_afbc_layouts == 0)) in komeda_get_format_caps()
28 return caps; in komeda_get_format_caps()
30 if (has_bits(afbc_features, caps->supported_afbc_features) && in komeda_get_format_caps()
31 has_bit(afbc_layout, caps->supported_afbc_layouts)) in komeda_get_format_caps()
32 return caps; in komeda_get_format_caps()
99 const struct komeda_format_caps *caps; in komeda_format_mod_supported() local
101 caps = komeda_get_format_caps(table, fourcc, modifier); in komeda_format_mod_supported()
[all …]
/linux/drivers/crypto/stm32/
H A Dstm32-cryp.c198 const struct stm32_cryp_caps *caps; member
308 return readl_relaxed_poll_timeout(cryp->regs + cryp->caps->sr, status, in stm32_cryp_wait_busy()
314 writel_relaxed(readl_relaxed(cryp->regs + cryp->caps->cr) | CR_CRYPEN, in stm32_cryp_enable()
315 cryp->regs + cryp->caps->cr); in stm32_cryp_enable()
322 return readl_relaxed_poll_timeout(cryp->regs + cryp->caps->cr, status, in stm32_cryp_wait_enable()
330 return readl_relaxed_poll_timeout_atomic(cryp->regs + cryp->caps->sr, status, in stm32_cryp_wait_input()
338 return readl_relaxed_poll_timeout_atomic(cryp->regs + cryp->caps->sr, status, in stm32_cryp_wait_output()
344 writel_relaxed(readl_relaxed(cryp->regs + cryp->caps->cr) | CR_KEYRDEN, in stm32_cryp_key_read_enable()
345 cryp->regs + cryp->caps->cr); in stm32_cryp_key_read_enable()
350 writel_relaxed(readl_relaxed(cryp->regs + cryp->caps->cr) & ~CR_KEYRDEN, in stm32_cryp_key_read_disable()
[all …]
/linux/drivers/vfio/pci/
H A Dvfio_pci_zdev.c23 static int zpci_base_cap(struct zpci_dev *zdev, struct vfio_info_cap *caps) in zpci_base_cap() argument
38 return vfio_info_add_capability(caps, &cap.header, sizeof(cap)); in zpci_base_cap()
44 static int zpci_group_cap(struct zpci_dev *zdev, struct vfio_info_cap *caps) in zpci_group_cap() argument
60 return vfio_info_add_capability(caps, &cap.header, sizeof(cap)); in zpci_group_cap()
66 static int zpci_util_cap(struct zpci_dev *zdev, struct vfio_info_cap *caps) in zpci_util_cap() argument
81 ret = vfio_info_add_capability(caps, &cap->header, cap_size); in zpci_util_cap()
91 static int zpci_pfip_cap(struct zpci_dev *zdev, struct vfio_info_cap *caps) in zpci_pfip_cap() argument
106 ret = vfio_info_add_capability(caps, &cap->header, cap_size); in zpci_pfip_cap()
117 struct vfio_info_cap *caps) in vfio_pci_info_zdev_add_caps() argument
125 ret = zpci_base_cap(zdev, caps); in vfio_pci_info_zdev_add_caps()
[all …]
/linux/drivers/mtd/nand/
H A Decc-mtk.c60 const struct mtk_ecc_caps *caps; member
146 dec = readw(ecc->regs + ecc->caps->ecc_regs[ECC_DECIRQ_STA]) in mtk_ecc_irq()
149 dec = readw(ecc->regs + ecc->caps->ecc_regs[ECC_DECDONE]); in mtk_ecc_irq()
155 readw(ecc->regs + ecc->caps->ecc_regs[ECC_DECIRQ_STA]); in mtk_ecc_irq()
162 enc = readl(ecc->regs + ecc->caps->ecc_regs[ECC_ENCIRQ_STA]) in mtk_ecc_irq()
178 for (i = 0; i < ecc->caps->num_ecc_strength; i++) { in mtk_ecc_config()
179 if (ecc->caps->ecc_strength[i] == config->strength) in mtk_ecc_config()
183 if (i == ecc->caps->num_ecc_strength) { in mtk_ecc_config()
195 reg = ecc_bit | (config->mode << ecc->caps->ecc_mode_shift); in mtk_ecc_config()
206 config->strength * ecc->caps->parity_bits; in mtk_ecc_config()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn303/
H A Ddcn303_resource.c761 &aux_engine_regs[inst], &aux_mask, &aux_shift, ctx->dc->caps.extended_aux_timeout_support); in dcn303_aux_engine_create()
1172 dc->caps.max_downscale_ratio = 600; in dcn303_resource_construct()
1173 dc->caps.i2c_speed_in_khz = 100; in dcn303_resource_construct()
1174 dc->caps.i2c_speed_in_khz_hdcp = 5; /*1.4 w/a applied by derfault*/ in dcn303_resource_construct()
1175 dc->caps.max_cursor_size = 256; in dcn303_resource_construct()
1176 dc->caps.min_horizontal_blanking_period = 80; in dcn303_resource_construct()
1177 dc->caps.dmdata_alloc_size = 2048; in dcn303_resource_construct()
1178 dc->caps.mall_size_per_mem_channel = 4; in dcn303_resource_construct()
1180 dc->caps.mall_size_total = dc->caps.mall_size_per_mem_channel * in dcn303_resource_construct()
1183 dc->caps.cursor_cache_size = in dcn303_resource_construct()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn302/
H A Ddcn302_resource.c803 &aux_engine_regs[inst], &aux_mask, &aux_shift, ctx->dc->caps.extended_aux_timeout_support); in dcn302_aux_engine_create()
1231 dc->caps.max_downscale_ratio = 600; in dcn302_resource_construct()
1232 dc->caps.i2c_speed_in_khz = 100; in dcn302_resource_construct()
1233 dc->caps.i2c_speed_in_khz_hdcp = 5; /*1.4 w/a applied by derfault*/ in dcn302_resource_construct()
1234 dc->caps.max_cursor_size = 256; in dcn302_resource_construct()
1235 dc->caps.min_horizontal_blanking_period = 80; in dcn302_resource_construct()
1236 dc->caps.dmdata_alloc_size = 2048; in dcn302_resource_construct()
1237 dc->caps.mall_size_per_mem_channel = 4; in dcn302_resource_construct()
1239 …dc->caps.mall_size_total = dc->caps.mall_size_per_mem_channel * dc->ctx->dc_bios->vram_info.num_ch… in dcn302_resource_construct()
1240 dc->caps.cursor_cache_size = dc->caps.max_cursor_size * dc->caps.max_cursor_size * 8; in dcn302_resource_construct()
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/linux/drivers/gpu/drm/amd/display/dc/dcn20/
H A Ddcn20_dwb.c50 static bool dwb2_get_caps(struct dwbc *dwbc, struct dwb_caps *caps) in dwb2_get_caps() argument
53 if (caps) { in dwb2_get_caps()
54 caps->adapter_id = 0; /* we only support 1 adapter currently */ in dwb2_get_caps()
55 caps->hw_version = DCN_VERSION_2_0; in dwb2_get_caps()
56 caps->num_pipes = 1; in dwb2_get_caps()
57 memset(&caps->reserved, 0, sizeof(caps->reserved)); in dwb2_get_caps()
58 memset(&caps->reserved2, 0, sizeof(caps->reserved2)); in dwb2_get_caps()
59 caps->sw_version = dwb_ver_1_0; in dwb2_get_caps()
60 caps->caps.support_dwb = true; in dwb2_get_caps()
61 caps->caps.support_ogam = false; in dwb2_get_caps()
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