Searched refs:cacheline_size (Results 1 – 10 of 10) sorted by relevance
7 int __pure cacheline_size(void);16 u64 size = cacheline_size(); in cl_address()27 u64 size = cacheline_size(); in cl_offset()
17 int cacheline_size(void) in cacheline_size() function
2486 int cln_size = cacheline_size(); in sort__typecln_sort()2514 int cln_size = cacheline_size(); in hist_entry__typecln_snprintf()3586 } else if (sd->entry == &sort_mem_dcacheline && cacheline_size() == 0) { in __sort_dimension__update()3834 if (!cacheline_size() && !strncasecmp(tok, "dcacheline", strlen(tok))) in setup_sort_list()
297 unsigned short cacheline_size; /* Bytes 104-105 */ member
413 enum myrs_cacheline_size cacheline_size; /* Byte 7 */ member
1575 if (ldev_info->cacheline_size) { in myrs_mode_sense()1577 put_unaligned_be16(1 << ldev_info->cacheline_size, in myrs_mode_sense()
4172 u8 cacheline_size; in pci_set_cacheline_size() local4179 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size); in pci_set_cacheline_size()4180 if (cacheline_size >= pci_cache_line_size && in pci_set_cacheline_size()4181 (cacheline_size % pci_cache_line_size) == 0) in pci_set_cacheline_size()4187 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size); in pci_set_cacheline_size()4188 if (cacheline_size == pci_cache_line_size) in pci_set_cacheline_size()
342 cache->cacheline_size); in kfd_cache_show()1643 pcache->cacheline_size = pcache_info[cache_type].cache_line_size; in fill_in_l1_pcache()1727 pcache->cacheline_size = pcache_info[cache_type].cache_line_size; in fill_in_l2_l3_pcache()
1197 props->cacheline_size = cache->cache_line_size; in kfd_parse_subtype_cache()
17113 int cacheline_size; in tg3_calc_dma_bndry() local17119 cacheline_size = 1024; in tg3_calc_dma_bndry()17121 cacheline_size = (int) byte * 4; in tg3_calc_dma_bndry()17161 switch (cacheline_size) { in tg3_calc_dma_bndry()17186 switch (cacheline_size) { in tg3_calc_dma_bndry()17203 switch (cacheline_size) { in tg3_calc_dma_bndry()